4c3715c2e5
Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84911 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 23:19:17 +00:00
bac6ed4ba4
Revert 84843. Evan, this was breaking some of the if-conversion tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84868 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 16:52:21 +00:00
87689d3b70
Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84843 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 06:48:32 +00:00
faf93aa233
Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84842 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 06:47:35 +00:00
62d1723a9c
Trim more includes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84832 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 05:11:00 +00:00
268c79350e
Trim include.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84831 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 05:08:49 +00:00
8000c6c535
Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84813 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 00:40:00 +00:00
41fff8c19a
Missing piece of the ARM frame index post-scavenging conditionalization
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84798 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 23:40:56 +00:00
1d6827bbe9
Conditionalize ARM/T2 frame index post-scavenging while working out fixes
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for a few bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84791 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 22:59:24 +00:00
20d108140e
Most of the NEON shuffle instructions do not support 64-bit element types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84785 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 21:36:27 +00:00
65b7f3af76
Improve handling of immediates by splitting 32-bit immediates into two 16-bit
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immediate operands when they will fit into the using instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84778 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 20:44:34 +00:00
b27b51aaa6
Fix NEON VST2LN instruction encoding.
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Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84767 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 17:54:01 +00:00
407d57489f
Revert 84732. It was the wrong fix.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84766 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 17:52:34 +00:00
2095659a85
Match more patterns to movt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84751 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 08:15:52 +00:00
1ce75ef5ef
tidy
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84738 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 04:10:24 +00:00
b3c8359360
Fix some more NEON instruction encoding problems.
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Thanks to Johnny Chen for discovering the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84732 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 02:27:20 +00:00
507df402b0
Leave some NEON instruction encoding bits unspecified instead of setting
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a default value of zero. This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84730 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 02:15:46 +00:00
a7cc65283a
Fix -Asserts warning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84687 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 22:10:05 +00:00
3229b0bcf1
Disable by default while debugging
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84669 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 20:31:31 +00:00
18ed9c9a2b
add cmd line opt to disable frame index reuse for ARM and T2. debug aid.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84664 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 20:19:50 +00:00
174101e13a
Random #include pruning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84632 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 11:44:38 +00:00
235e2f6a68
implement some more easy hooks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84614 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 06:22:33 +00:00
bf16faa16a
Implement some hooks, make printOperand abort if unknown modifiers are
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present.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84613 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 06:15:28 +00:00
c6b8a99207
t2MOVi32imm is currently always lowered by the Thumb2ITBlockPass.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84611 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 05:58:02 +00:00
2685a29a8d
Wire up the ARM MCInst printer, for llvm-mc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84600 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 05:15:36 +00:00
8fa4efeabf
Now that all ARM subtargets use frame index scavenging, the Thumb1 requires*
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functions are not needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84587 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 01:32:47 +00:00
7e831db1d4
Enable post-pass frame index register scavenging for ARM and Thumb2
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84585 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 01:26:58 +00:00
161dcbf799
lower ARM::MOVi32imm properly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84583 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 01:11:37 +00:00
292df8eb1f
add support for external symbols. The mc instprinter can now handle
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reasonable code like Codegen/ARM/2009-02-27-SpillerBug.ll, producing
identical output except for superior formatting of constant pool entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84582 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 00:56:16 +00:00
96bc2173bb
get fancy: support basic block operands. Yay for jumps.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84579 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 00:52:47 +00:00
233917c072
add supprort for the 'sbit' operand, MOVi apparently has one.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84577 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 00:46:11 +00:00
413ae25fb5
add support for instruction predicates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84575 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 00:42:49 +00:00
017d9478d5
implement printSORegOperand, add lowering for the nasty and despicable MOVi2pieces :)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84573 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 00:40:56 +00:00
1fc1dc0682
Refs: A8-598.
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Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.
Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84572 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 00:38:19 +00:00
780d207d1c
Add missing encoding bits to NLdSt class of instructions.
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Patch by Johnny Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84570 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-20 00:19:08 +00:00
306d14f9aa
handle addmode4 modifiers, fix a fixme in printRegisterList
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by ignoring all implicit regs when lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84566 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 23:31:43 +00:00
6009751244
Enable allocation of R3 in Thumb1
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84563 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 22:57:03 +00:00
5a207897bc
use EmitLabel instead of text emission
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84562 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 22:51:16 +00:00
7c5b021793
add a twine version of MCContext::GetOrCreateSymbol.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84561 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 22:49:00 +00:00
a70e644820
lower the ARM::CONSTPOOL_ENTRY pseudo op, giving us constant pool entries
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like:
@ BB#1:
.align 2
LCPI1_0:
.long L_.str-(LPC0+8)
Note that proper indentation of the label :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84558 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 22:33:05 +00:00
d482f55af1
Adjust the scavenge register spilling to allow the target to choose an
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appropriate restore location for the spill as well as perform the actual
save and restore.
The Thumb1 target uses this to make sure R12 is not clobbered while a spilled
scavenger register is live there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84554 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 22:27:30 +00:00
4d15222341
add MCInstLower support for lowering ARM::PICADD, a pseudo op for pic stuffola.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84553 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 22:23:04 +00:00
e306d8d6cc
add register list and hacked up addrmode #4 support, we now get this:
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_main:
stmsp! sp!, {r7, lr}
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0, [sp]
ldr r0, LCPI1_0
bl _printf
ldr r0, [sp]
mov sp, r7
ldmsp! sp!, {r7, pc}
Note the unhappy ldm/stm because of modifiers being ignored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84546 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 22:09:23 +00:00
084f87d445
add addrmode2 support, getting us up to:
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_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0, [sp]
ldr r0, LCPI1_0
bl _printf
ldr r0, [sp]
mov sp, r7
ldm ,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84543 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 21:57:05 +00:00
6f99776f6c
add jump tables, constant pools and some trivial global
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lowering stuff. We can now compile hello world to:
_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0,
ldr r0,
bl _printf
ldr r0,
mov sp, r7
ldm ,
Almost looks like arm code :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84542 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 21:53:00 +00:00
8514e21deb
reduce #includes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84536 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 21:23:15 +00:00
61d35c273e
add printing support for SOImm operands, getting us to:
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_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84535 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 21:21:39 +00:00
8bc86cba60
wire up some basic printOperand goodness, giving us stuff like this before
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we abort:
_main:
stm ,
mov r7, sp
sub sp, sp,
mov r0,
str r0,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84532 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 20:59:55 +00:00
9cf0eb5e58
add the files that go with the previous rev
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84531 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 20:21:05 +00:00
97f0693744
wire up skeletal support for having llc print instructions
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through mcinst lowering -> mcinstprinter, when llc is passed
the -enable-arm-mcinst-printer flag. Currently this
is very "aborty".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84530 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 20:20:46 +00:00
David Goodwin
Bob Wilson
Evan Cheng
Jim Grosbach
Chris Lattner
Daniel Dunbar
Benjamin Kramer