Commit Graph

24054 Commits

Author SHA1 Message Date
Hao Liu
1c2f863df9 AArch64/ARM64: Port NEON post-increment load/store with 2/3/4 vectors to ARM64 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208284 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 07:38:13 +00:00
Saleem Abdulrasool
f6efab64b4 test: fix silly typo
Oh silly Darwin and your case insensitive file system.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208274 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 01:41:04 +00:00
Saleem Abdulrasool
dade1d5db5 ARM: support FK_SecRel_2 relocations on WoA
This adds FK_SecRel_2 relocation support to ARM.  This enables the building of
object files for armv7-windows-msvc which enables CodeView line tables for
debugging as opposed to armv7-windows-itanium which currently uses DWARF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208273 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 01:35:57 +00:00
Filipe Cabecinhas
b19c087aa7 Lower certain build_vectors to insertps instructions
Summary:
Vectors built with zeros and elements in the same order as another
(source) vector are optimized to be built using a single insertps
instruction.
Also optimize when we move one element in a vector to a different place
in that vector while zeroing out some of the other elements.

Further optimizations are possible, described in TODO comments.
I will be implementing at least some of them in the near future.

Added some tests for different cases where this optimization triggers.

Reviewers: nadav, delena, craig.topper

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3521

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208271 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08 00:25:16 +00:00
Duncan P. N. Exon Smith
76c17d324c IR: Don't allow non-default visibility on local linkage
Visibilities of `hidden` and `protected` are meaningless for symbols
with local linkage.

  - Change the assembler to reject non-default visibility on symbols
    with local linkage.

  - Change the bitcode reader to auto-upgrade `hidden` and `protected`
    to `default` when the linkage is local.

  - Update LangRef.

<rdar://problem/16141113>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208263 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 22:57:20 +00:00
Quentin Colombet
57b4c5d473 [X86] Add a test case for r208252.
Prior to r208252, the FMA 231 family was marked as isCommutable. However the
memory variants of this family are not commutable. Therefore, we did not
implemented the findCommutedOpIndices for those variants and missed that
the default implementation (more or less: commute indices 1 and 2) was
firing behind our back.
As a result, as demonstrated in the test case before the fix, we were
transforming a = b * c + a into a = a * c + b.

I.e., before r208252 we were generating for this test case:
vmovaps %xmm0, %xmm1
vmoss (%rsi), %xmm0
vfmadd231ss (%rdi), %xmm1, %xmm0

Instead of:
vmoss (%rsi), %xmm1
vfmadd231ss (%rdi), %xmm1, %xmm0

<rdar://problem/16800495> 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208260 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 22:52:58 +00:00
Adam Nemet
a822fab74d [Test] Remove c-index-test from the list of substitutions
All the tests are under the clang tests and none should be under llvm moving
forward.

The topic was discussed in this thread:

http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140428/214905.html

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208234 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 18:16:02 +00:00
Sebastian Pop
5026b2cc8b split delinearization pass in 3 steps
To compute the dimensions of the array in a unique way, we split the
delinearization analysis in three steps:

- find parametric terms in all memory access functions
- compute the array dimensions from the set of terms
- compute the delinearized access functions for each dimension

The first step is executed on all the memory access functions such that we
gather all the patterns in which an array is accessed. The second step reduces
all this information in a unique description of the sizes of the array. The
third step is delinearizing each memory access function following the common
description of the shape of the array computed in step 2.

This rewrite of the delinearization pass also solves a problem we had with the
previous implementation: because the previous algorithm was by induction on the
structure of the SCEV, it would not correctly recognize the shape of the array
when the memory access was not following the nesting of the loops: for example,
see polly/test/ScopInfo/multidim_only_ivs_3d_reverse.ll

; void foo(long n, long m, long o, double A[n][m][o]) {
;
;   for (long i = 0; i < n; i++)
;     for (long j = 0; j < m; j++)
;       for (long k = 0; k < o; k++)
;         A[i][k][j] = 1.0;

Starting with this patch we no longer delinearize access functions that do not
contain parameters, for example in test/Analysis/DependenceAnalysis/GCD.ll

;;  for (long int i = 0; i < 100; i++)
;;    for (long int j = 0; j < 100; j++) {
;;      A[2*i - 4*j] = i;
;;      *B++ = A[6*i + 8*j];

these accesses will not be delinearized as the upper bound of the loops are
constants, and their access functions do not contain SCEVUnknown parameters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208232 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 18:01:20 +00:00
Simon Atanasyan
d92c843b2e [yaml2obj] Support ELF x86 relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208228 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 17:06:38 +00:00
Chad Rosier
8f0f458824 [ARM64][fast-isel] Disable target specific optimizations at -O0. Functionally,
this patch disables the dead register elimination pass and the load/store pair
optimization pass at -O0.  The ILP optimizations don't require the optimization
level to be checked because the call to addILPOpts is predicated with the
necessary check.  The AdvSIMDScalar pass is disabled by default at all
optimization levels.  This patch leaves that pass disabled by default.

Also, move command-line options into ARM64TargetMachine.cpp and add a few
additional flags to aid in debugging.  This fixes an issue with the
-debug-pass=Structure flag where passes were printed, but not actually run
(i.e., AdvSIMDScalar pass).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208223 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 16:41:55 +00:00
Daniel Sanders
7858e495e9 [mips] Add highly experimental support for MIPS-I, MIPS-II, MIPS-III, and MIPS-V
Summary:
These processors will only be available for the integrated assembler at
first (CodeGen will emit a fatal error saying they are not implemented).

The intention is to work through the existing instructions and correctly
annotate the ISA they were added in so that we have a sufficiently good
base to start MIPS64r6 development. MIPS64r6 removes/re-encodes certain
instructions and I believe it is best to define ISA's using set-union's
as far as possible rather than using set-subtraction.

Reviewers: vmedic

Subscribers: emaste, llvm-commits

Differential Revision: http://reviews.llvm.org/D3569

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208221 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 16:25:22 +00:00
Michael Zolotukhin
355e0a6460 [InstCombine] Add optimization of redundant insertvalue instructions.
rdar://problem/11861387

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208214 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 14:30:18 +00:00
Evgeniy Stepanov
8a387a7aee [msan] Fix -fsanitize=memory -fno-integrated-as.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208211 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 14:10:51 +00:00
Tim Northover
04a359f768 AArch64/ARM64: optimise vector selects & enable test
When performing a scalar comparison that feeds into a vector select,
it's actually better to do the comparison on the vector side: the
scalar route would be "CMP -> CSEL -> DUP", the vector is "CM -> DUP"
since the vector comparisons are all mask based.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208210 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 14:10:27 +00:00
James Molloy
2712c87cfe [ARM64-BE] Fix fast-isel, and add appropriate RUN lines to appropriate tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208200 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 12:33:55 +00:00
James Molloy
d93d214a67 [ARM64-BE] Fix variable-argument saving.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208199 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 12:33:48 +00:00
James Molloy
fca7f5c585 [ARM64-BE] Implement the lane-twiddling logic at AAPCS boundaries for big endian.
The AAPCS states that values passed in registers must have a value as though
they had been loaded with "LDR". LDR is equivalent to "LD1.64 vX.1D" - that is,
loading scalars to vector registers and loading 1-element vectors is equivalent.

The logic implemented here is to ensure that at all call boundaries and during
formal argument lowering all vectors are treated as their bitwidth-based floating
point scalar counterpart, which is always one of f64 or f128 (v2i32 -> f64,
v4i32 -> f128 etc). A BITCAST is inserted so that the appropriate REV will be
generated during code generation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208198 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 12:33:41 +00:00
James Molloy
737c2ac4fc [ARM64-BE] Implement the crazy bitcast handling for big endian vectors.
Because we've canonicalised on using LD1/ST1, every time we do a bitcast
between vector types we must do an equivalent lane reversal.

Consider a simple memory load followed by a bitconvert then a store.
  v0 = load v2i32
  v1 = BITCAST v2i32 v0 to v4i16
       store v4i16 v2

In big endian mode every memory access has an implicit byte swap. LDR and
STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
is, they treat the vector as a sequence of elements to be byte-swapped.
The two pairs of instructions are fundamentally incompatible. We've decided
to use LD1/ST1 only to simplify compiler implementation.

LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
the original code sequence:  v0 = load v2i32

  v1 = REV v2i32                  (implicit)
  v2 = BITCAST v2i32 v1 to v4i16
  v3 = REV v4i16 v2               (implicit)
       store v4i16 v3

But this is now broken - the value stored is different to the value loaded
due to lane reordering. To fix this, on every BITCAST we must perform two
other REVs:

  v0 = load v2i32
  v1 = REV v2i32                  (implicit)
  v2 = REV v2i32
  v3 = BITCAST v2i32 v2 to v4i16
  v4 = REV v4i16
  v5 = REV v4i16 v4               (implicit)
       store v4i16 v5

This means an extra two instructions, but actually in most cases the two REV
instructions can be combined into one. For example:
  (REV64_2s (REV64_4h X)) === (REV32_4h X)

There is also no 128-bit REV instruction. This must be synthesized with an
EXT instruction.

Most bitconverts require some sort of conversion. The only exceptions are:
  a) Identity conversions -  vNfX <-> vNiX
  b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX

Even though there are hundreds of changed lines, I have a fairly high confidence
that they are somewhat correct. The changes to add two REV instructions per
bitcast were pretty mechanical, and once I'd done that I threw the resulting
.td at a script I wrote which combined the two REVs together (and added
an EXT instruction, for f128) based on an instruction description I gave it.

This was much less prone to error than doing it all manually, plus my brain
would not just have melted but would have vapourised.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208194 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 11:28:53 +00:00
James Molloy
104629cc7c [ARM64-BE] Make big endian (scalar) argument passing work correctly.
This completes the port of r204814 (cpirker "AArch64_BE function argument
passing for ARM ABI") from AArch64 to ARM64, and fixes a bunch of issues
found during later development along the way. The biggest of these was
that the alignment fixup logic wasn't replicated into all the places it
should have been.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208192 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 11:28:36 +00:00
Tim Northover
0d427515b3 AArch64/ARM64: run test on ARM64 too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208188 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 10:47:04 +00:00
Tim Northover
5a1d5139b8 AArch64/ARM64: put annotation in test
It makes finding already covered tests much easier with "grep -L
arm64".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208187 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 10:47:00 +00:00
Tim Northover
c6f683627d AArch64/ARM64: disable test directory if ARM64 not present
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208186 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 10:42:06 +00:00
Daniel Sanders
d80222a48b [tablegen] Add !listconcat operator with the similar semantics as !strconcat
Summary:
It concatenates two or more lists. In addition to the !strconcat semantics
the lists must have the same element type.

My overall aim is to make it easy to append to Instruction.Predicates
rather than override it. This can be done by concatenating lists passed as
arguments, or by concatenating lists passed in additional fields.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: hfinkel, llvm-commits

Differential Revision: http://reviews.llvm.org/D3506

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208183 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 10:13:19 +00:00
Evgeniy Stepanov
227c4c6185 [asan] Add a flag to control asm instrumentation.
With this change, asm instrumentation is disabled by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208167 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 07:54:11 +00:00
Joerg Sonnenberger
2ecdcdc026 Allow using normal .eh_frame based unwinding on ARM. Use the same
encodings as x86. Use this exception model for NetBSD.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208166 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 07:49:34 +00:00
Saleem Abdulrasool
0029e2d665 ARM: fix WoA PEI instruction selection
The ARM::BLX instruction is an ARM mode instruction.  The Windows on ARM target
is limited to Thumb instructions.  Correctly use the thumb mode tBLXr
instruction.  This would manifest as an errant write into the object file as the
instruction is 4-bytes in length rather than 2.  The result would be a corrupted
object file that would eventually result in an executable that would crash at
runtime.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208152 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 03:03:27 +00:00
Justin Bogner
c92330c18c llvm-cov: Handle missing source files as GCOV does
If the source files referenced by a gcno file are missing, gcov
outputs a coverage file where every line is simply /*EOF*/.  This also
occurs for lines in the coverage that are past the end of a file that
is found.

This change mimics gcov.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208149 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 02:11:23 +00:00
Justin Bogner
56d05e468c llvm-cov: Implement --no-output
In gcov, there's a -n/--no-output option, which disables the writing
of any .gcov files, so that it emits only the summary info on stdout.
This implements the same behaviour in llvm-cov.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208148 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07 02:11:18 +00:00
Joerg Sonnenberger
b84f890bc3 If a function needs a frame pointer, but r11 (aka fp) has not been used,
remove it from the list of unspilled registers. Otherwise the following
attempt to keep the stack aligned by picking an extra GPR register to
spill will not work as it picks up r11.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208129 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 20:43:01 +00:00
Diego Novillo
e3e870face Do not make -pass-remarks additive.
Summary:
When I initially introduced -pass-remarks, I thought it would be a
neat idea to make it additive. So, if one used it as:

$ llc -pass-remarks=inliner --pass-remarks=loop.*

the compiler would build the regular expression '(inliner)|(loop.*)'.

The more I think about it, the more I regret it. This is not how
other flags work. The standard semantics are right-to-left overrides.

This is how clang interprets -Rpass. And I think the two should be
compatible in this respect.

Reviewers: qcolombet

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3614

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208122 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 19:14:00 +00:00
Benjamin Kramer
2c06cd8612 TTI: Estimate @llvm.fmuladd cost as fmul + fadd when FMA's aren't legal on the target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208115 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 18:36:23 +00:00
Andrea Di Biagio
8a712ba229 [X86] Improve the lowering of BITCAST dag nodes from type f64 to type v2i32 (and vice versa).
Before this patch, the backend always emitted a store+load sequence to
bitconvert from f64 to i64 the input operand of a ISD::BITCAST dag node that
performed a bitconvert from type MVT::f64 to type MVT::v2i32. The resulting
i64 node was then used to build a v2i32 vector.

With this patch, the backend now produces a cheaper SCALAR_TO_VECTOR from
MVT::f64 to MVT::v2f64. That SCALAR_TO_VECTOR is then followed by a "free"
bitcast to type MVT::v4i32. The elements of the resulting
v4i32 are then extracted to build a v2i32 vector (which is illegal and
therefore promoted to MVT::v2i64).

This is in general cheaper than emitting a stack store+load sequence
to bitconvert the operand from type f64 to type i64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208107 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 17:09:03 +00:00
Renato Golin
22f779d1fd Implememting named register intrinsics
This patch implements the infrastructure to use named register constructs in
programs that need access to specific registers (bare metal, kernels, etc).

So far, only the stack pointer is supported as a technology preview, but as it
is, the intrinsic can already support all non-allocatable registers from any
architecture.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208104 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 16:51:25 +00:00
Rafael Espindola
b889448841 Special case aliases in GlobalValue::getAlignment.
An alias has the address of what it points to, so it also has the same
alignment.

This allows a few optimizations to see past aliases for free.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208103 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 16:48:58 +00:00
Tim Northover
3524723195 AArch64/ARM64: implement diagnosis of unpredictable loads & stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208091 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 14:15:14 +00:00
Tim Northover
4d28f030f7 AArch64/ARM64: add two more MC tests to ARM64 set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208085 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 12:50:58 +00:00
Tim Northover
c08733f867 AArch64/ARM64: enable MC-level diagnostic tests for NEON insts.
Obviously we can't expect the two backends to produce identical diagnostics,
since what's possible depends quite a bit on how the .td files are structured.
I think the ARM64 diagnostics are basically of the same quality in all the
changed cases, so I've split the CHECK lines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208084 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 12:50:55 +00:00
Tim Northover
09b3bd8ca3 AArch64/ARM64: make NEON vector list parsing a bit more robust
It doesn't change the results, but it seems silly not to diagnose obvious
problems early on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208083 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 12:50:51 +00:00
Tim Northover
6e64f90dc5 AArch64/ARM64: produce more informative diagnostic assembling some immediates
No tests here, they'll be added when the entire neon-diagnostics.s test from
AArch64 is enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208079 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 11:18:53 +00:00
Christian Pirker
80fd09110d ARM: For thumb fixups store halfwords high first and low second
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208076 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 10:05:11 +00:00
Kevin Qin
03145ebd88 [ARM64] Enable alignment control option in front-end for ARM64.
This is the modification in llvm part.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208074 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 09:48:52 +00:00
Reid Kleckner
9ad48c11b1 Fix i128 div/mod on mingw64
The Win64 docs are very clear that anything larger than 8 bytes is
passed by reference, and GCC MinGW64 honors that for __modti3 and
friends.

Patch by Jameson Nash!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208029 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 01:20:42 +00:00
Nick Lewycky
05da4dd998 Improve 'tail' call marking in TRE. A bootstrap of clang goes from 375k calls marked tail in the IR to 470k, however this improvement does not carry into an improvement of the call/jmp ratio on x86. The most common pattern is a tail call + br to a block with nothing but a 'ret'.
The number of tail call to loop conversions remains the same (1618 by my count).

The new algorithm does a local scan over the use-def chains to identify local "alloca-derived" values, as well as points where the alloca could escape. Then, a visit over the CFG marks blocks as being before or after the allocas have escaped, and annotates the calls accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208017 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-05 23:59:03 +00:00
Tom Stellard
4b84b524e5 R600: Expand i64 ISD:SUB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208005 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-05 21:47:15 +00:00
Filipe Cabecinhas
75ea413a1b Revert "Optimize shufflevector that copies an i64/f64 and zeros the rest."
This reverts commit 207992. I misread the phab number on the LGTM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207993 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-05 19:40:36 +00:00
Filipe Cabecinhas
a0fa9eb606 Optimize shufflevector that copies an i64/f64 and zeros the rest.
Summary:
Also ran clang-format on the function. The code added is the last else
if block.

Reviewers: nadav, craig.topper

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3518

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207992 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-05 19:36:28 +00:00
Michael Zolotukhin
830195e5fb Move test from r207969 to another folder and rename it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207984 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-05 18:10:15 +00:00
Yi Jiang
606660f1f3 Always set alignment of vectorized LD/ST in SLP-Vectorizer. <rdar://problem/16812145>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207983 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-05 17:59:14 +00:00
Joerg Sonnenberger
b85d6905b5 Fix spelling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207982 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-05 17:58:46 +00:00
Duncan P. N. Exon Smith
bbd9c21e07 LTO: -internalize sets visibility to default
Visibility is meaningless when the linkage is local.  Change
`-internalize` to reset the visibility to `default`.

<rdar://problem/16141113>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207979 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-05 17:40:44 +00:00