Jim Grosbach
7b25ecf6ad
ARM BL/BLX instruction fixups should use relocations.
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We on the linker to resolve calls to the appropriate BL/BLX instruction
to make interworking function correctly. It uses the symbol in the
relocation to do that, so we need to be careful about being too clever.
To enable this for ARM mode, split the BL/BLX fixup kind off from the
unconditional-branch fixups.
rdar://10927209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151571 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27 21:36:23 +00:00
Craig Topper
930a1ebd92
X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151510 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-27 01:54:29 +00:00
Michael J. Spencer
32d22ee11d
Emit global ctors into .CRT$XCU instead of .ctors on Win32. Patch by Joe Groff!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151289 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 21:56:08 +00:00
Kevin Enderby
b80d571ea8
Updated the llvm-mc disassembler C API to support for the X86 target.
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rdar://10873652
As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there is no getOpInfo call back. If there is a
getOpInfo call back that is tried first and then if that gets no information
then the SymbolLookUp is called. I also made the code more robust by
memset(3)'ing to zero the LLVMOpInfo1 struct before then setting
SymbolicOp.Value before for the call to getOpInfo. And also don't use any
values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't
use any of the ReferenceType or ReferenceName values from SymbolLookUp if it
returns NULL. rdar://10873563 and rdar://10873683
For the X86 target also fixed bugs so the annotations get printed.
Also fixed a few places in the ARM target that was not producing symbolic
operands for some instructions. rdar://10878166
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151267 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 18:18:17 +00:00
Craig Topper
28a713b20a
Add vmfunc instruction to X86 assembler and disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150899 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-19 01:39:49 +00:00
Craig Topper
9e3d0b3351
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150873 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-18 08:19:49 +00:00
Eli Bendersky
0f0c411079
Replace all instances of dg.exp file with lit.local.cfg, since all tests are run with LIT now and now Dejagnu. dg.exp is no longer needed.
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Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16 06:28:33 +00:00
David Meyer
5f7692604d
For ELF, also call fixSymbolsInTLSFixups() on expressions passed to EmitValue (literal values). Previously only called on expressions in instructions. New test cases added to tls.s, tls-i386.s. Resolves PR11981.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150582 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15 15:09:06 +00:00
James Molloy
3015dfb7d7
Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150169 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09 10:56:31 +00:00
Kevin Enderby
d49b2a7a9d
Fixed a crash in llvm-mc for Mach-O when a symbol difference expression uses a
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symbol from an assignment. In this case the symbol did not have a fragment so
MCObjectWriter::IsSymbolRefDifferenceFullyResolved() should not have been
calling IsSymbolRefDifferenceFullyResolvedImpl() with a NULL fragment and should
just have returned false in that case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149442 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-31 23:02:57 +00:00
Devang Patel
885f65b4a1
Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,sd,ps,pd}, for intel syntax.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149291 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30 22:47:12 +00:00
Devang Patel
be3e310d5e
Intel syntax. Support .intel_syntax directive.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149270 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30 20:02:42 +00:00
James Molloy
2d8955a77c
Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM and MIPS ELF backends.
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Fixes PR11877
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149180 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-28 15:58:32 +00:00
Rafael Espindola
8b01c82f25
Small improvement to the recursion detection logic from the previous commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149175 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-28 06:22:14 +00:00
Rafael Espindola
e71cc86ad1
Handle recursive variable definitions directly. This gives us better error
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messages and allows us to fix PR11865.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149174 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-28 05:57:00 +00:00
Devang Patel
a28101e61a
Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149142 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-27 19:48:28 +00:00
James Molloy
34982576a4
Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors.
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This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149057 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-26 09:25:43 +00:00
Jim Grosbach
74423e32ce
ARM assemly parsing and validation of IT instruction.
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"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."
PR11853
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2012-01-25 19:52:01 +00:00
Jim Grosbach
a57a36abe7
NEON VLD4(all lanes) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148884 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 00:01:08 +00:00
Jim Grosbach
5e59f7e15e
NEON VLD3(all lanes) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148882 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 23:47:04 +00:00
Jim Grosbach
c389af94b6
ARM Darwin symbol ref differences w/o subsection-via-symbols.
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When not using subsections via symbols, the assembler can resolve
symbol differences (including pcrel references) to non-local
labels at assembly time, not just those in the same atom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148865 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 21:45:25 +00:00
Devang Patel
3b96e1fe3b
Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148864 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 21:43:36 +00:00
Jim Grosbach
88a54de799
NEON VST4(one lane) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148836 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 18:53:13 +00:00
Jim Grosbach
e983a134e7
NEON VLD4(one lane) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148832 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 18:37:25 +00:00
Jim Grosbach
1ac2060678
NEON Two-operand assembly aliases for VSRA.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148821 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 17:55:36 +00:00
Jim Grosbach
5d9bad4098
Remove redundant test file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148820 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 17:55:32 +00:00
Jim Grosbach
5e497d3992
NEON Two-operand assembly aliases for VSLI.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148819 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 17:49:15 +00:00
Jim Grosbach
d8ee0cc4e8
NEON Two-operand assembly aliases for VSRI.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148818 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 17:46:58 +00:00
Jim Grosbach
28f1f9100f
Tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148817 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 17:46:54 +00:00
Jim Grosbach
539aab771f
NEON VST4(multiple 4 element structures) assembly parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148764 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 00:58:13 +00:00
Jim Grosbach
8abe7e3364
NEON VLD4(multiple 4 element structures) assembly parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148762 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 00:43:17 +00:00
Jim Grosbach
4adb182342
NEON VST3(single element from one lane) assembly parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148755 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 00:07:41 +00:00
Jim Grosbach
d7433e2873
NEON VST3(multiple 3-element structures) assembly parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148748 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 23:45:44 +00:00
Jim Grosbach
c387fc66bd
NEON VLD3(multiple 3-element structures) assembly parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148745 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 23:20:46 +00:00
Devang Patel
f2d213745e
Intel syntax: Robustify parsing of memory operand's displacement experssion.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148737 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 22:35:25 +00:00
Jim Grosbach
3a678af71d
NEON VLD3 lane-indexed assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148734 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 21:53:26 +00:00
Rafael Espindola
16d7d437e0
Add support for .cfi_signal_frame. Fixes pr11762.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148733 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 21:51:52 +00:00
Devang Patel
3e08131185
Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148721 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 20:20:06 +00:00
Jim Grosbach
8b31f95bdd
Simplify some NEON assembly pseudo definitions.
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Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148718 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 19:39:08 +00:00
Devang Patel
7c64fe651a
Intel syntax: Parse segment registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 18:31:58 +00:00
Devang Patel
1aea430b88
Intel syntax: Robustify register parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148591 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 22:32:05 +00:00
Devang Patel
fdd3b30151
Intel syntax: Parse ... PTR [-8]
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148570 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 21:21:01 +00:00
Devang Patel
cf0e269d16
Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148569 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 21:14:06 +00:00
Jim Grosbach
51222d1551
NEON use vmov.i32 to splat some f32 values into vectors.
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For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.
rdar://10616677
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 18:09:51 +00:00
Devang Patel
a951f77ca3
Post process 'and', 'sub' instructions and select better encoding, if available.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148489 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 18:40:55 +00:00
Devang Patel
e60540f380
Intel syntax: There is no need to create unary expr for simple negative displacement.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148486 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 18:15:51 +00:00
Devang Patel
ac0f048602
Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148485 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 17:53:25 +00:00
Jim Grosbach
904b7be27e
Add testcase.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148454 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 01:36:59 +00:00
Jim Grosbach
0b4c673886
Thumb2 alternate syntax for LDR(literal) and friends.
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Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".
rdar://10250964
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148432 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18 22:46:46 +00:00
Devang Patel
b8ba13f009
Process instructions after match to select alternative encoding which may be more desirable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148431 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18 22:42:29 +00:00