Christopher Lamb
2330e4d4c4
add support for alignment attributes on load/store instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36301 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-21 08:16:25 +00:00
Lauro Ramos Venancio
0d3b67809c
Allow the lowering of ISD::GLOBAL_OFFSET_TABLE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36290 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-20 23:02:39 +00:00
Lauro Ramos Venancio
b3a0417cad
Implement "general dynamic", "initial exec" and "local exec" TLS models for
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X86 32 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36283 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-20 21:38:10 +00:00
Chris Lattner
61a4c072b9
allow SRL to simplify its operands, as it doesn't demand all bits as input.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36245 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-18 03:06:49 +00:00
Chris Lattner
ec06e9a670
When replacing a node in SimplifyDemandedBits, if the old node used any
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single-use nodes, they will be dead soon. Make sure to remove them before
processing other nodes. This implements CodeGen/X86/shl_elim.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36244 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-18 03:05:22 +00:00
Chris Lattner
0a16a1f738
fix a pasto
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36242 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-18 03:01:40 +00:00
Chris Lattner
8c7d2d56bf
Fix a bug in my previous patch, grabbing the shift amount width from the
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wrong operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36223 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-17 22:53:02 +00:00
Chris Lattner
895c4ab564
Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used.
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This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }
into:
_baz:
srwi r2, r3, 1
extsh r3, r2
blr
on PPC, instead of:
_baz:
slwi r2, r3, 8
srwi r2, r2, 9
extsh r3, r2
blr
GCC produces:
_baz:
srwi r10,r4,24
insrwi r10,r3,24,0
srawi r9,r3,24
srawi r3,r10,9
extsh r3,r3
blr
This implements CodeGen/PowerPC/shl_elim.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36221 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-17 21:14:16 +00:00
Chris Lattner
95a5e0507e
SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBits
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a chance to hack on it. This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }
into:
_baz:
slwi r2, r3, 8
srwi r2, r2, 9
extsh r3, r2
blr
instead of:
_baz:
srwi r2, r4, 24
rlwimi r2, r3, 8, 0, 23
srwi r2, r2, 9
extsh r3, r2
blr
This implements CodeGen/PowerPC/sign_ext_inreg1.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36212 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-17 19:03:21 +00:00
Anton Korobeynikov
bed2946a96
Removed tabs everywhere except autogenerated & external files. Add make
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target for tabs checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36146 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-16 18:10:23 +00:00
Chris Lattner
1c35968d4d
disable switch lowering using shift/and. It still breaks ppc bootstrap for
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some reason. :( Will investigate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36011 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-14 19:39:41 +00:00
Anton Korobeynikov
e01017bba4
Fix PR1325: Case range optimization was performed in the case it
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shouldn't. Also fix some "latent" bug on 64-bit platforms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35990 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-14 13:25:55 +00:00
Chris Lattner
3ff981749b
disable shift/and lowering to work around PR1325 for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35985 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-14 02:26:56 +00:00
Anton Korobeynikov
8085bcfdca
Fix PR1323 : we haven't updated phi nodes in good manner :)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35963 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-13 06:53:51 +00:00
Chris Lattner
3a508c94a6
the result of an inline asm copy can be an arbitrary VT that the register
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class supports. In the case of vectors, this means we often get the wrong
type (e.g. we get v4f32 instead of v8i16). Make sure to convert the vector
result to the right type. This fixes CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35944 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-12 06:00:20 +00:00
Chris Lattner
4829b1c6ab
fold noop vbitconvert instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35943 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-12 05:58:43 +00:00
Chris Lattner
c2941779c3
Fix weirdness handling single element vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35941 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-12 04:44:28 +00:00
Reid Spencer
f75b874957
For PR1284:
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Implement the "part_set" intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35938 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-12 02:48:46 +00:00
Chris Lattner
c24bbaddf8
fix an infinite loop compiling ldecod, notice by JeffC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35910 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11 16:51:53 +00:00
Chris Lattner
1eba01e9a0
Fix this harder.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35888 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11 06:50:51 +00:00
Chris Lattner
c56a81dff1
don't create shifts by zero, fix some problems with my previous patch
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35887 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11 06:43:25 +00:00
Chris Lattner
20a35c3fa5
Teach the codegen to turn [aez]ext (setcc) -> selectcc of 1/0, which often
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allows other simplifications. For example, this compiles:
int isnegative(unsigned int X) {
return !(X < 2147483648U);
}
Into this code:
x86:
movl 4(%esp), %eax
shrl $31, %eax
ret
arm:
mov r0, r0, lsr #31
bx lr
thumb:
lsr r0, r0, #31
bx lr
instead of:
x86:
cmpl $0, 4(%esp)
sets %al
movzbl %al, %eax
ret
arm:
mov r3, #0
cmp r0, #0
movlt r3, #1
mov r0, r3
bx lr
thumb:
mov r2, #1
mov r1, #0
cmp r0, #0
blt LBB1_2 @entry
LBB1_1: @entry
cpy r2, r1
LBB1_2: @entry
cpy r0, r2
bx lr
Testcase here: test/CodeGen/Generic/ispositive.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35883 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11 05:32:27 +00:00
Chris Lattner
1982ef20c4
Codegen integer abs more efficiently using the trick from the PPC CWG. This
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improves codegen on many architectures. Tests committed as CodeGen/*/iabs.ll
X86 Old: X86 New:
_test: _test:
movl 4(%esp), %ecx movl 4(%esp), %eax
movl %ecx, %eax movl %eax, %ecx
negl %eax sarl $31, %ecx
testl %ecx, %ecx addl %ecx, %eax
cmovns %ecx, %eax xorl %ecx, %eax
ret ret
PPC Old: PPC New:
_test: _test:
cmpwi cr0, r3, -1 srawi r2, r3, 31
neg r2, r3 add r3, r3, r2
bgt cr0, LBB1_2 ; xor r3, r3, r2
LBB1_1: ; blr
mr r3, r2
LBB1_2: ;
blr
ARM Old: ARM New:
_test: _test:
rsb r3, r0, #0 add r3, r0, r0, asr #31
cmp r0, #0 eor r0, r3, r0, asr #31
movge r3, r0 bx lr
mov r0, r3
bx lr
Thumb Old: Thumb New:
_test: _test:
neg r2, r0 asr r2, r0, #31
cmp r0, #0 add r0, r0, r2
bge LBB1_2 eor r0, r2
LBB1_1: @ bx lr
cpy r0, r2
LBB1_2: @
bx lr
Sparc Old: Sparc New:
test: test:
save -96, %o6, %o6 save -96, %o6, %o6
sethi 0, %l0 sra %i0, 31, %l0
sub %l0, %i0, %l0 add %i0, %l0, %l1
subcc %i0, -1, %l1 xor %l1, %l0, %i0
bg .BB1_2 restore %g0, %g0, %g0
nop retl
.BB1_1: nop
or %g0, %l0, %i0
.BB1_2:
restore %g0, %g0, %g0
retl
nop
It also helps alpha/ia64 :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35881 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11 05:11:38 +00:00
Reid Spencer
18da072088
For PR1146:
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Put the parameter attributes in their own ParamAttr name space. Adjust the
rest of llvm as a result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35877 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11 02:44:20 +00:00
Chris Lattner
c6eb6d7255
apparently some people commit without building the tree, or they forget to
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commit a LOT of files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35858 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-10 03:20:39 +00:00
Jeff Cohen
2da8da46ba
No longer needed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35850 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 23:42:32 +00:00
Chris Lattner
2b95fd67da
remove dead target hooks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35847 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 23:34:08 +00:00
Chris Lattner
b445d0cbb9
remove some dead target hooks, subsumed by isLegalAddressingMode
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35840 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 22:27:04 +00:00
Anton Korobeynikov
54e2b142be
Use integer log for metric calculation
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35834 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 21:57:03 +00:00
Jeff Cohen
efc3662636
Unbreak VC++ build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35817 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 14:32:59 +00:00
Anton Korobeynikov
4198c58c71
Next stage into switch lowering refactoring
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1. Fix some bugs in the jump table lowering threshold
2. Implement much better metric for optimal pivot selection
3. Tune thresholds for different lowering methods
4. Implement shift-and trick for lowering small (<machine word
length) cases with few destinations. Good testcase will follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35816 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 12:31:58 +00:00
Reid Spencer
5694b6e90e
For PR1146:
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Adapt handling of parameter attributes to use the new ParamAttrsList class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35814 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 06:17:21 +00:00
Chris Lattner
1a6acc214d
implement CodeGen/X86/inline-asm-x-scalar.ll:test3
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35802 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 05:31:20 +00:00
Chris Lattner
ff33cc4d08
add some assertions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35800 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 05:23:13 +00:00
Chris Lattner
4b993b19f9
Fix PR1316
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35783 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 00:33:58 +00:00
Chris Lattner
921169b103
Fix for CodeGen/X86/2007-04-08-InlineAsmCrash.ll and PR1314
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35779 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-08 22:23:26 +00:00
Chris Lattner
e303ac9052
minor comment fix
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35696 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-06 17:47:14 +00:00
Reid Spencer
3f108cb555
Change the bit_part_select (non)implementation from "return 0" to abort.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35679 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-05 01:20:18 +00:00
Reid Spencer
addd11d98e
Implement the llvm.bit.part_select.iN.iN.iN overloaded intrinsic.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35678 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-04 23:48:25 +00:00
Anton Korobeynikov
5502bf67cd
Properly emit range comparisons for switch cases, where neighbour cases
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go to the same destination. Now we're producing really good code for
switch-lower-feature.ll testcase
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35672 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-04 21:14:49 +00:00
Scott Michel
c9dc114578
1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL.
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2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL
patterns. This was motivated by the X86/rotate.ll testcase, which should now
generate code for other platforms (and soon-to-come platforms.) Rewrote code
slightly to make it easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35605 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-02 21:36:32 +00:00
Reid Spencer
a4f9c4d29a
For PR1297:
...
Adjust for changes in the bit counting intrinsics. They all return i32
now so we have to trunc/zext the DAG node accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35546 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-01 07:34:11 +00:00
Reid Spencer
577cc32d9a
For PR1297:
...
Change getOperationName to return std::string instead of const char*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35545 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-01 07:32:19 +00:00
Chris Lattner
c8d288f8fa
move a bunch of code out of the sdisel pass into its own opt pass "codegenprepare".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35529 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-31 04:18:03 +00:00
Chris Lattner
d2f340b746
switch TL::getValueType to use MVT::getValueType.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35527 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-31 04:05:24 +00:00
Chris Lattner
1436bb657d
add one addressing mode description hook to rule them all.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35520 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-30 23:14:50 +00:00
Dale Johannesen
2041a0ef75
Fix incorrect combination of different loads. Reenable zext-over-truncate
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combination.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35517 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-30 21:38:07 +00:00
Evan Cheng
b0b6c76ffe
Disable load width reduction xform of variant (zext (truncate load x)) for
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big endian targets until llvm-gcc build issue has been resolved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35449 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-29 07:56:46 +00:00
Evan Cheng
7aff11a1ed
Scale 1 is always ok.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35407 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-28 01:55:52 +00:00
Evan Cheng
caaf69107e
Remove isLegalAddressImmediate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35406 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-28 01:53:55 +00:00