Chris Lattner
7df31dc89b
Teach the dag scheduler to handle inline asm nodes with multi-value immediate operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41386 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-25 00:53:07 +00:00
Evan Cheng
33d5595d66
Do not emit copies for physical register output if it's not used.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40722 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-02 05:29:38 +00:00
Evan Cheng
8409747efa
Instead of adding copyfromreg's to handle physical definitions. Now isel can
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simply specify them as results and let scheduledag handle them. That
is, instead of
SDOperand Flag = DAG.getTargetNode(Opc, MVT::i32, MVT::Flag, ...)
SDOperand Result = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, Flag)
Just write:
SDOperand Result = DAG.getTargetNode(Opc, MVT::i32, MVT::i32, ...)
And let scheduledag emit the move from X86::EAX to a virtual register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40710 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-02 00:28:15 +00:00
Christopher Lamb
e24f8f1ec9
Teach DAG scheduling how to properly emit subreg insert/extract machine instructions. PR1350
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40520 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-26 08:12:07 +00:00
Dale Johannesen
e7e7d0d7e3
Skeleton of post-RA scheduler; doesn't do anything yet.
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Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39816 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-13 17:13:54 +00:00
Evan Cheng
5e2456c959
If the operand is marked M_OPTIONAL_DEF_OPERAND, then it's a def.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38496 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-10 17:52:20 +00:00
Evan Cheng
af825c840e
When a node value is only used by a CopyToReg, use the user's dest. This should not be restricted to nodes that produce only a single value.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38485 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-10 07:08:32 +00:00
Evan Cheng
991262834d
Change CalculateHeights and CalculateDepths to be non-recursive.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37934 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-06 01:37:28 +00:00
Dan Gohman
b5bec2b6f6
Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration
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for needing the DAG node to print pre-legalize extended value types, and
to get better debug messages with target-specific nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37656 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-19 14:13:56 +00:00
Jeff Cohen
c01a53007a
Fix some VC++ warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35224 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-20 20:43:18 +00:00
Lauro Ramos Venancio
a0a26b7454
Code clean up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35220 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-20 20:09:03 +00:00
Lauro Ramos Venancio
8334b9fa3b
CopyToReg source operand can be a physical register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35213 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-20 16:46:44 +00:00
Chris Lattner
95ad943ed5
print target nodes nicely
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34369 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-17 06:38:37 +00:00
Chris Lattner
5d4a9f7731
fix indentation
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34307 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-15 18:19:15 +00:00
Chris Lattner
0152829e89
Apply B Scott Michel's patch for PR1184, which improves diagnostics in an
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abort case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34306 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-15 18:17:56 +00:00
Reid Spencer
ac9dcb94dd
For PR1195:
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Change use of "packed" term to "vector" in comments, strings, variable
names, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34300 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-15 03:39:18 +00:00
Chris Lattner
831e0374a7
switch the VRBaseMap in the scheduler from an std::map to a DenseMap. This
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speeds up the isel pass from 2.5570s to 2.4722s on kc++ (3.4%).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33879 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-04 08:47:20 +00:00
Jim Laskey
1ee2925742
Make LABEL a builtin opcode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-26 14:34:52 +00:00
Evan Cheng
de268f7dcf
Renamed getTypeAlignmentShift() to getPreferredTypeAlignmentShift().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33482 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-24 07:03:39 +00:00
Evan Cheng
f6d039a039
Remove the DoubleTy special case.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33449 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-22 23:13:55 +00:00
Reid Spencer
e5530da208
Compensate for loss of DerivedTypes.h in TargetLowering.h
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33159 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-12 23:31:12 +00:00
Evan Cheng
489a87ca09
CopyToReg source operand can be a register as well. e.g. Copy from GlobalBaseReg.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32929 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-05 20:59:06 +00:00
Bill Wendling
832171cb97
Removing even more <iostream> includes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32320 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-07 20:04:42 +00:00
Evan Cheng
ba59a1e453
Match TargetInstrInfo changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32098 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-01 21:52:58 +00:00
Evan Cheng
c0f64ffab9
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
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of opcode and number of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-27 23:37:22 +00:00
Evan Cheng
7ce4578353
Matches MachineInstr changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31712 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-13 23:36:35 +00:00
Evan Cheng
3ba433a7e8
Add methods to add implicit def use operands to a MI.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31675 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-11 10:20:02 +00:00
Evan Cheng
438f7bc67c
Add implicit def / use operands to MachineInstr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31633 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-10 08:43:01 +00:00
Evan Cheng
95f6edeff5
Changes to use operand constraints to process two-address instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31453 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-04 09:44:31 +00:00
Chris Lattner
efa46ce87b
handle global address constant sdnodes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31323 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-31 20:01:56 +00:00
Evan Cheng
d42a5238a9
Debug tweak.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30959 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-14 08:34:06 +00:00
Evan Cheng
d6594ae54c
Added support for machine specific constantpool values. These are useful for
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representing expressions that can only be resolved at link time, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30278 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-12 21:00:35 +00:00
Chris Lattner
09e460662a
Completely eliminate def&use operands. Now a register operand is EITHER a
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def operand or a use operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30109 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-05 02:31:13 +00:00
Chris Lattner
228a18e0f2
switch the SUnit pred/succ sets from being std::sets to being smallvectors.
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This reduces selectiondag time on kc++ from 5.43s to 4.98s (9%). More
significantly, this speeds up the default ppc scheduler from ~1571ms to 1063ms,
a 33% speedup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29743 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-17 00:09:56 +00:00
Evan Cheng
3b97acdbdb
Reverse the FlaggedNodes after scanning up for flagged preds or else the order would be reversed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29545 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-07 22:12:12 +00:00
Jim Laskey
60f09928a0
Use an enumeration to eliminate data relocations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29249 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-21 20:57:35 +00:00
Jim Laskey
16d42c6ac6
It was pointed out that DEBUG() is only available with -debug.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29106 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-11 18:25:13 +00:00
Jim Laskey
e37fe9b3a1
Ensure that dump calls that are associated with asserts are removed from
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non-debug build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29105 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-11 17:58:07 +00:00
Evan Cheng
8d3af5e7d0
Instructions with variable operands (variable_ops) can have a number required
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operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
"call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.
Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28791 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-15 07:22:16 +00:00
Evan Cheng
4c6f2f9e92
commuteInstruction() does not always create a new MI!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28592 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-31 18:03:39 +00:00
Evan Cheng
16eee25c66
Eliminate a memory leak.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28585 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-31 07:13:03 +00:00
Evan Cheng
21d03f2de0
lib/Target/Target.td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28386 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-18 20:42:07 +00:00
Chris Lattner
966454129d
Move function-live-in-handling code from the sdisel code to the scheduler.
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This code should be emitted after legalize, so it can't be in sdisel.
Note that the EmitFunctionEntryCode hook should be updated to operate on the
DAG. The X86 backend is the only one currently using this hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28315 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-16 06:10:58 +00:00
Evan Cheng
8820ad5154
Fixing 2006-05-01-SchedCausingSpills.ll; some clean up
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28279 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-13 08:22:24 +00:00
Owen Anderson
07000c6f01
Refactor a bunch of includes so that TargetMachine.h doesn't have to include
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TargetData.h. This should make recompiles a bit faster with my current
TargetData tinkering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28238 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-12 06:33:49 +00:00
Evan Cheng
626da3d9ae
Duh. That could take a long time.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28235 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-12 06:05:18 +00:00
Evan Cheng
13d41b9d72
Add capability to scheduler to commute nodes for profit.
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If a two-address code whose first operand has uses below, it should be commuted
when possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28230 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-12 01:58:24 +00:00
Evan Cheng
e165a78551
Refactor scheduler code. Move register-reduction list scheduler to a
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separate file. Added an initial implementation of top-down register pressure
reduction list scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28226 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-11 23:55:42 +00:00
Chris Lattner
8b915b4ed2
Remove and simplify some more machineinstr/machineoperand stuff.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28105 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-04 18:16:01 +00:00
Chris Lattner
2d90ac7ca6
Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28104 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-04 18:05:43 +00:00