Commit Graph

125 Commits

Author SHA1 Message Date
Kalle Raiskila
18aa393153 Don't feed 19 bit immediates to ILA.
Patch (slightly modified) by Visa Putkinen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122052 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17 09:36:09 +00:00
Devang Patel
afeaae7a94 If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121059 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06 22:39:26 +00:00
Kalle Raiskila
9363f739cd Handle lshr for i128 correctly on SPU also when
shiftamount > 7.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120288 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 14:44:28 +00:00
Kalle Raiskila
c2ebfd454c Enable PostRA scheduling for SPU.
This speeds up selected test cases with up to
5% - no slowdowns observed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120286 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29 10:30:25 +00:00
Kalle Raiskila
702a4046a9 Allow for 'fcmp ogt' in SPU.
Fix by Visa Putkinen!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120090 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-24 11:42:17 +00:00
Kalle Raiskila
0cc5b1f60e Division by pow-of-2 is not cheap on SPU, do it with
shifts.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120022 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-23 13:27:59 +00:00
Kalle Raiskila
d87e571e62 Fix a bug with extractelement on SPU.
In the attached testcase, the element was
never extracted (missing rotate).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119973 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-22 16:28:26 +00:00
Kalle Raiskila
7ea1ab5f41 Fix memory access lowering on SPU, adding
support for the case where alignment<value size.

These cases were silently miscompiled before this patch.
Now they are overly verbose -especially storing is- and
any front-end should still avoid misaligned memory 
accesses as much as possible. The bit juggling algorithm
added here probably has some room for improvement still.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118889 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12 10:14:03 +00:00
Kalle Raiskila
505faa6b12 Change v64 datalayout in SPU.
The SPU ABI does not mention v64, and all examples
in C suggest v128 are treated similarily to arrays, 
we use array alignment for v64 too. This makes the 
alignment of e.g. [2 x <2 x i32>] behave "intuitively"
and similar to as if the elements were e.g. i32s.

This also makes an "unaligned store" test to be 
aligned, with different (but functionally equivalent)
code generated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-26 10:45:47 +00:00
Kalle Raiskila
940e7965f1 Improve lowering of sext to i128 on SPU.
The old algorithm inserted a 'rotqmbyi' instruction which was
both redundant and wrong - it made shufb select bytes from the
wrong end of the input quad.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116701 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 09:34:19 +00:00
Kalle Raiskila
8258135c90 Zap some redundant 'ori $?, $?, 0' from SPU.
Also remove some code that died in the process.
One now non-existant ori is checked for.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115306 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-01 09:20:01 +00:00
Kalle Raiskila
1cd1b0b283 Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.
This cleans up after the mess r108567 left in the CellSPU backend.
ORCvt-instruction were used to reinterpret registers, and the ORs were then
removed by isMoveInstr(). This patch now removes 350 instrucions of format:
	or $3, $3, $3
(from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is
checked for.

Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114074 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 12:29:33 +00:00
Kalle Raiskila
0b4ab0cfe0 Fix CellSPU vector shuffles, again.
Some cases of lowering to rotate were miscompiled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113355 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 11:53:38 +00:00
Kalle Raiskila
bd887df8b9 Fix lowering of INSERT_VECTOR_ELT in SPU.
The IDX was treated as byte index, not element index.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112422 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29 12:41:50 +00:00
Kalle Raiskila
55aebef654 Fix SPU BE to use all the available return registers.
llc used to assert on the added testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111911 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 11:50:48 +00:00
Kalle Raiskila
ca9460f5a0 Fix a bug with insertelement on SPU.
The previous algorithm in LowerVECTOR_SHUFFLE 
didn't check all requirements for "monotonic" shuffles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111361 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 10:20:29 +00:00
Kalle Raiskila
86a791284a Remove all traces of v2[i,f]32 on SPU.
The "half vectors" are now widened to full size by the legalizer.
The only exception is in parameter passing, where half vectors are 
expanded. This causes changes to some dejagnu tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 10:04:39 +00:00
Kalle Raiskila
44ff5f5435 Change SPU C calling convention to match that described in
"SPU Application Binary Interface Specification, v1.9" by
IBM. 
Specifically: use r3-r74 to pass parameters and the return value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 09:50:30 +00:00
Kalle Raiskila
99534bb81a Have SPU handle halfvec stores aligned by 8 bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110576 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-09 16:33:00 +00:00
Kalle Raiskila
bc2697cca0 Make SPU backend handle insertelement and
store for "half vectors"


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110198 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-04 13:59:48 +00:00
Kalle Raiskila
e1c9159f63 More SPU v2f32 stuff added: insertelement and shuffle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110038 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-02 11:22:10 +00:00
Kalle Raiskila
c9fda996fc Add preliminary v2f32 support for SPU. Like with v2i32, we just
duplicate the instructions and operate on half vectors. 

Also reorder code in SPUInstrInfo.td for better coherency.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110037 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-02 10:25:47 +00:00
Kalle Raiskila
82fe467ca5 Add preliminary v2i32 support for SPU backend. As there are no
such registers in SPU, this support boils down to "emulating" 
them by duplicating instructions on the general purpose registers. 

This adds the most basic operations on v2i32: passing parameters,
addition, subtraction, multiplication and a few others.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110035 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-02 08:54:39 +00:00
Jakob Stoklund Olesen
04c528a0c8 Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway.
TII::isMoveInstr is going tobe completely removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108507 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 04:45:42 +00:00
Benjamin Kramer
a2938e7e5f Fix some tests that didn't test anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106954 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26 20:05:06 +00:00
Kalle Raiskila
2e39498114 Add the check to the testcase of r106419.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 15:11:51 +00:00
Kalle Raiskila
951b229ccf Mark the SPU 'lr' instruction to never have side effects.
This allows the fast regiser allocator to remove redundant 
register moves.
Update a set of tests that depend on the register allocator
to be linear scan. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106420 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 15:08:16 +00:00
Kalle Raiskila
91fdee125c Fix the lowering of VECTOR_SHUFFLE on SPU to handle splats.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106419 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 14:42:19 +00:00
Kalle Raiskila
4794807134 Fix lowering of VECTOR_SHUFFLE on SPU. Old algorithm
used to choke llc with the attached test.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106411 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 10:17:36 +00:00
Kalle Raiskila
43d225dc8b Fix SPU to cope with vector insertelement to an undef position.
We default to inserting to lane 0.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105722 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09 09:58:17 +00:00
Kalle Raiskila
c6166c6bca Handle loading from/storing to undef pointers on SPU by inserting a
random load/store, rather than crashing llc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09 08:29:41 +00:00
Kalle Raiskila
11fe24624a Fix handling of 'load' nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105269 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-01 13:34:47 +00:00
Kalle Raiskila
2320a44b90 Make SPU backend not assert on jump tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103466 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 11:00:02 +00:00
Kalle Raiskila
26c4cf4c6f Fix encoding of 'sf' and 'sfh' instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103399 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-10 08:13:49 +00:00
Chris Lattner
d4ac35b350 "on the rare occasion the SPU BE produces illegal assembly - it tries to emit an add instruction of the form 'a reg, reg, imm'."
Patch by Kalle Raiskila!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 17:58:46 +00:00
Chris Lattner
aa2776e934 teach cellspu how to return i8 and i16 from calls,
patch by Kalle Raiskila!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 05:36:09 +00:00
Benjamin Kramer
232c8b4d26 Make sure this test tests something.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09 19:03:31 +00:00
Chris Lattner
dc8446330f "On SPU, variables in the .bss section that are allocated with the .lcomm directive are not aligned on 16 byte boundaries. This causes misaligned loads, as the generated assembly assumes this "default" alignment.
this patch disables .lcomm in favour of '.local .comm'

Patch by Kalle Raisklia!




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09 18:27:03 +00:00
Dale Johannesen
b39b7e5ebf Split big test into multiple directories to cater to
those who don't build all targets.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100688 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 20:43:35 +00:00
Chris Lattner
e27e02b1a4 From Kalle Raiskila:
"the bigstack patch for SPU, with testcase. It is essentially the patch committed as 97091, and reverted as 97099, but with the following additions:
-in vararg handling, registers are marked to be live, to not confuse the register scavenger
-function prologue and epilogue are not emitted, if the stack size is 16. 16 means it is empty - there is only the register scavenger emergency spill slot, which is not used as there is no stack."



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99819 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-29 17:38:47 +00:00
Chris Lattner
ac834e7a5f fix bss section printing for cell, patch by Kalle Raiskila!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97814 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-05 18:55:36 +00:00
Chris Lattner
41aa25a433 don't let asm-verbose break the check-next lines in these tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93869 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-19 06:39:54 +00:00
Evan Cheng
d40d03e1bd Teach dag combine to fold the following transformation more aggressively:
(OP (trunc x), (trunc y)) -> (trunc (OP x, y))

Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel.

This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92849 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-06 19:38:29 +00:00
Dan Gohman
aceba31b7a Delete useless trailing semicolons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92740 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-05 17:55:26 +00:00
Evan Cheng
4c2b001f13 Revert this dag combine change:
Fold (zext (and x, cst)) -> (and (zext x), cst)

DAG combiner likes to optimize expression in the other way so this would end up cause an infinite looping.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91574 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-17 00:40:05 +00:00
Evan Cheng
8acb3100de Fold (zext (and x, cst)) -> (and (zext x), cst).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91380 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-15 00:52:11 +00:00
Evan Cheng
7bd6478cd6 Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 isl lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90925 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-09 01:53:58 +00:00
Dan Gohman
6d31268a7d Revert the main portion of r31856. It was causing BranchFolding
to break up CFG diamonds by banishing one of the blocks to the end of
the function, which is bad for code density and branch size.

This does pessimize MultiSource/Benchmarks/Ptrdist/yacr2, the
benchmark cited as the reason for the change, however I've examined
the code and it looks more like a case of gaming a particular
branch than of being generally applicable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84803 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 00:03:58 +00:00
Daniel Dunbar
068c56e0d7 Teach lit that the .c files in 'test/CodeGen/CellSPU/useful-harnesses' aren't tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84460 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-19 03:53:55 +00:00
Dan Gohman
b7c0b246da Convert more tests to avoid llvm-as.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81545 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-11 18:36:27 +00:00