Commit Graph

2586 Commits

Author SHA1 Message Date
Evan Cheng
358dec5180 Part 1.
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 08:28:29 +00:00
Evan Cheng
e7d6df7353 Add a ARM specific pre-allocation pass that re-schedule loads / stores from
consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.

This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73291 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-13 09:12:55 +00:00
Evan Cheng
4a274e573d If killed register is defined by implicit_def, do not clear it since it's live range may overlap another def of same register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73255 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-12 21:34:26 +00:00
Evan Cheng
cd799b99cb Mark some pattern-less instructions as neverHasSideEffects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73252 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-12 20:46:18 +00:00
Arnold Schwaighofer
bbd8c33ee6 Fix Bug 4278: X86-64 with -tailcallopt calling convention
out of sync with regular cc.

The only difference between the tail call cc and the normal
cc was that one parameter register - R9 - was reserved for
calling functions through a function pointer. After time the
tail call cc has gotten out of sync with the regular cc. 

We can use R11 which is also caller saved but not used as
parameter register for potential function pointers and
remove the special tail call cc on x86-64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73233 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-12 16:26:57 +00:00
Anton Korobeynikov
f194b0edc9 Add testcase for register scanveger assertion fix in r72755
(double def due to livevars)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73096 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-08 22:54:15 +00:00
Eli Friedman
faeedf1254 Fix the run-line for this test to work correctly outside of x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73025 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-07 09:44:19 +00:00
Eli Friedman
f10d3a7bcd Tweak the expansion code for BIT_CONVERT to generate better code
converting from an MMX vector to an i64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73024 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-07 09:41:57 +00:00
Eli Friedman
7a5e55509b Slightly generalize the code that handles shuffles of consecutive loads
on x86 to handle more cases.  Fix a bug in said code that would cause it 
to read past the end of an object.  Rewrite the code in 
SelectionDAGLegalize::ExpandBUILD_VECTOR to be a bit more general. 
Remove PerformBuildVectorCombine, which is no longer necessary with 
these changes.  In addition to simplifying the code, with this change, 
we can now catch a few more cases of consecutive loads.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73012 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-07 06:52:44 +00:00
Eli Friedman
0da9975299 PR3628: Add patterns to match SHL/SRL/SRA to the corresponding Altivec
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73009 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-07 01:07:55 +00:00
Eli Friedman
5257106c4d Fix the expansion for CONCAT_VECTORS so that it doesn't create illegal
types.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72993 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-06 07:08:26 +00:00
Eli Friedman
30e71eb61b Avoid crashing on a variable-index insertelement with element type i16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72991 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-06 06:32:50 +00:00
Eli Friedman
1041553424 Get rid of some bogus patterns for X86vzmovl. Don't create VZEXT_MOVL
nodes for vectors with an i16 element type.  Add an optimization for 
building a vector which is all zeros/undef except for the bottom 
element, where the bottom element is an i8 or i16.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72988 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-06 06:05:10 +00:00
Eli Friedman
9d47b8d8ea Fix an obvious typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72987 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-06 05:55:37 +00:00
Eli Friedman
1762c1439e Get rid of a bogus pattern that interferes with optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72985 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-06 04:17:04 +00:00
Eli Friedman
23ef105580 PR2598: make sure to expand illegal forms of integer/floating-point
conversions for x86, like <2 x i32> -> <2 x float> and <4 x i16> -> 
<4 x float>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72983 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-06 03:57:58 +00:00
Nate Begeman
abc0199680 Adapt the x86 build_vector dagcombine to the current state of the legalizer.
build vectors with i64 elements will only appear on 32b x86 before legalize.
Since vector widening occurs during legalize, and produces i64 build_vector 
elements, the dag combiner is never run on these before legalize splits them
into 32b elements.

Teach the build_vector dag combine in x86 back end to recognize consecutive 
loads producing the low part of the vector.

Convert the two uses of TLI's consecutive load recognizer to pass LoadSDNodes
since that was required implicitly.

Add a testcase for the transform.

Old:
	subl	$28, %esp
	movl	32(%esp), %eax
	movl	4(%eax), %ecx
	movl	%ecx, 4(%esp)
	movl	(%eax), %eax
	movl	%eax, (%esp)
	movaps	(%esp), %xmm0
	pmovzxwd	%xmm0, %xmm0
	movl	36(%esp), %eax
	movaps	%xmm0, (%eax)
	addl	$28, %esp
	ret

New:
	movl	4(%esp), %eax
	pmovzxwd	(%eax), %xmm0
	movl	8(%esp), %eax
	movaps	%xmm0, (%eax)
	ret




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72957 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05 21:37:30 +00:00
Evan Cheng
925492279a Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72955 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05 19:08:58 +00:00
Dan Gohman
9f5f322a03 Fix an erroneous check for isFNeg; the FNeg case is handled
a few lines later on.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72904 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 23:43:29 +00:00
Dan Gohman
ae3a0be92e Split the Add, Sub, and Mul instruction opcodes into separate
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 22:49:04 +00:00
Devang Patel
d18e31ae17 Add new function attribute - noredzone.
Update code generator to use this attribute and remove DisableRedZone target option.
Update llc to set this attribute when -disable-red-zone command line option is used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72894 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 22:05:33 +00:00
Evan Cheng
073e7e5807 RALinScan::attemptTrivialCoalescing() was returning a virtual register instead of the physical register it is allocated to. This resulted in virtual register(s) being added the live-in sets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72890 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 20:53:36 +00:00
Evan Cheng
cd0c4ac7fb A value defined by an implicit_def can be liven to a use BB. This is unfortunate. But register allocator still has to add it to the live-in set of the use BB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72888 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 20:25:48 +00:00
Dan Gohman
0e19a3f89e Check in test changes that I accidentally left out of r72872.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72875 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 18:22:31 +00:00
Eli Friedman
bccf4b3050 PR3739, part 2: Use an explicit store to spill XMM registers. (Previously,
the code tried to use "push", which doesn't exist for XMM registers.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72836 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 02:32:04 +00:00
Eli Friedman
9a41712122 PR3739, part 1: Disable the red zone on Win64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72830 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 02:02:01 +00:00
Evan Cheng
1488326156 Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72826 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 01:15:28 +00:00
Eli Friedman
a8ba2c25e9 PR4317: Handle splits where the new block is unreachable correctly in
DominatorTreeBase::Split.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72810 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03 21:42:06 +00:00
Evan Cheng
424f8f339a For Darwin / x86_64, override -relocation-model=static to pic if the output is assembly since Darwin assembler does not really support -static codeine.
I view this as a temporary workaround until the assembler / linker changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72806 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03 21:13:54 +00:00
Evan Cheng
2c48fe6757 Fix for PR4225: When rewriter reuse a value in a physical register , it clear the register kill operand marker and its kill ops information. However, the cleared operand may be a def of a super-register. Clear the kill ops info for the super-register's sub-registers as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72758 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03 09:00:27 +00:00
Evan Cheng
70fd60bd57 Temporarily revert 72756 for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72757 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03 07:40:47 +00:00
Evan Cheng
9d5fb981b0 Fold preceding / trailing base inc / dec into the single load / store as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72756 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03 06:14:58 +00:00
Dan Gohman
6ecc2602a6 Revert r72734. The Darwin assembler doesn't support the static
relocation model on x86-64. Higher level logic should override
the relocation model to PIC on x86_64-apple-darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72746 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03 00:37:20 +00:00
Dan Gohman
8b0d4f61bb Fix CodeGenPrepare's address-mode sinking to handle unusual
addresses, involving Base values which do not have Pointer type.
This fixes PR4297.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72739 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-02 21:29:13 +00:00
Evan Cheng
da9863fa41 On Darwin x86_64 small code model doesn't guarantee code address fits in 32-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72734 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-02 20:09:31 +00:00
Evan Cheng
cf7895ff8b (i64 (zext (srl GR32 8))) -> movzbl AH is not safe since srl 8 only clear the top 8 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72618 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-30 08:43:27 +00:00
Evan Cheng
8e610a7784 Remove an accidental commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72560 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-29 05:28:52 +00:00
Evan Cheng
cb219f0ef6 More h-registers tricks: folding zext nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72558 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-29 01:44:43 +00:00
Evan Cheng
d3c76bb6fc Do not try to create a MVT type of width 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72557 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28 23:52:18 +00:00
Eli Friedman
f1f7c09390 Add explicit test for PR4280.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72539 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28 21:04:35 +00:00
Eli Friedman
b999a7056e Add a testcase which got fixed by recent legalization work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72517 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28 05:10:20 +00:00
Evan Cheng
8b944d39b3 Added optimization that narrow load / op / store and the 'op' is a bit twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code.
e.g.
orl     $65536, 8(%rax)
=>
orb     $1, 10(%rax)

Since narrowing is not always a win, e.g. i32 -> i16 is a loss on x86, dag combiner consults with the target before performing the optimization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72507 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-28 00:35:15 +00:00
Bill Wendling
4ff5047240 This looks like it passes now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72485 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-27 17:43:21 +00:00
Torok Edwin
6bb4958543 Fix PR4254.
The DAGCombiner created a negative shiftamount, stored in an
unsigned variable. Later the optimizer eliminated the shift entirely as being
undefined.
Example: (srl (shl X, 56) 48). ShiftAmt is 4294967288.
Fix it by checking that the shiftamount is positive, and storing in a signed
variable.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72331 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-23 17:29:48 +00:00
Torok Edwin
f5ff1d335b available_externall linkage is not local, this was confusing the codegenerator,
and it wasn't generating calls through @PLT for these functions.
hasLocalLinkage() is now false for available_externally,
I attempted to fix the inliner and dce to handle available_externally properly.
It passed make check.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72328 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-23 14:06:57 +00:00
Eli Friedman
d14ce2f1fc Fix test to account for legalization changes; I think this ends up
running an extra DAGCombine pass which improves the code a bit.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72326 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-23 13:15:11 +00:00
Duncan Sands
b0f1e1780c Add a new codegen pass that normalizes dwarf exception handling
code in preparation for code generation.  The main thing it does
is handle the case when eh.exception calls (and, in a future
patch, eh.selector calls) are far away from landing pads.  Right
now in practice you only find eh.exception calls close to landing
pads: either in a landing pad (the common case) or in a landing
pad successor, due to loop passes shifting them about.  However
future exception handling improvements will result in calls far
from landing pads:
(1) Inlining of rewinds.  Consider the following case:
In function @f:
...
  invoke @g to label %normal unwind label %unwinds
...
unwinds:
  %ex = call i8* @llvm.eh.exception()
...

In function @g:
...
  invoke @something to label %continue unwind label %handler
...
handler:
  %ex = call i8* @llvm.eh.exception()
... perform cleanups ...
  "rethrow exception"

Now inline @g into @f.  Currently this is turned into:
In function @f:
...
  invoke @something to label %continue unwind label %handler
...
handler:
  %ex = call i8* @llvm.eh.exception()
... perform cleanups ...
  invoke "rethrow exception" to label %normal unwind label %unwinds
unwinds:
  %ex = call i8* @llvm.eh.exception()
...

However we would like to simplify invoke of "rethrow exception" into
a branch to the %unwinds label.  Then %unwinds is no longer a landing
pad, and the eh.exception call there is then far away from any landing
pads.

(2) Using the unwind instruction for cleanups.
It would be nice to have codegen handle the following case:
  invoke @something to label %continue unwind label %run_cleanups
...
handler:
... perform cleanups ...
  unwind

This requires turning "unwind" into a library call, which
necessarily takes a pointer to the exception as an argument
(this patch also does this unwind lowering).  But that means
you are using eh.exception again far from a landing pad.

(3) Bugpoint simplifications.  When bugpoint is simplifying
exception handling code it often generates eh.exception calls
far from a landing pad, which then causes codegen to assert.
Bugpoint then latches on to this assertion and loses sight
of the original problem.

Note that it is currently rare for this pass to actually do
anything.  And in fact it normally shouldn't do anything at
all given the code coming out of llvm-gcc!  But it does fire
a few times in the testsuite.  As far as I can see this is
almost always due to the LoopStrengthReduce codegen pass
introducing pointless loop preheader blocks which are landing
pads and only contain a branch to another block.  This other
block contains an eh.exception call.  So probably by tweaking
LoopStrengthReduce a bit this can be avoided.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72276 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-22 20:36:31 +00:00
Eli Friedman
2ac8b324eb Fix for PR4235: to build a floating-point value from integer parts,
build an integer and cast that to a float.  This fixes a crash 
caused by trying to split an f32 into two f16's.

This changes the behavior in test/CodeGen/XCore/fneg.ll because that 
testcase now triggers a DAGCombine which converts the fneg into an integer
operation.  If someone is interested, it's probably possible to tweak 
the test to generate an actual fneg.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72162 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-20 06:02:09 +00:00
Evan Cheng
c7d167d62f Fix test on non-darwin hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72161 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-20 05:45:36 +00:00
Evan Cheng
d7f666a869 Try again. Allow call to immediate address for ELF or when in static relocation mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72160 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-20 04:53:57 +00:00