Commit Graph

2395 Commits

Author SHA1 Message Date
Quentin Colombet
1ad3a410be ARM: Fix encoding of hint instruction for Thumb.
"hint" space for Thumb actually overlaps the encoding space of the CPS
instruction. In actuality, hints can be defined as CPS instructions where imod
and M bits are all nil.

Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe,
sev) in DecodeT2CPSInstruction.

This commit adds a proper diagnostic message for Imm0_4 and updates all tests.

Patch by Mihail Popa <Mihail.Popa@arm.com>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180617 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 17:54:54 +00:00
Jack Carter
97265a4889 Mips assembler: .set reorder support
Mips have delayslots for certain instructions 
like jumps and branches. These are instructions 
that follow the branch or jump and are executed
before the jump or branch is completed.

Early Mips compilers could not cope with delayslots
and left them up to the assembler. The assembler would
fill the delayslots with the appropriate instruction,
usually just a nop to allow correct runtime behavior.

The default behavior for this is set with .set reorder.
To tell the assembler that you don't want it to mess with
the delayslot one used .set noreorder.

For backwards compatibility we need to support
.set reorder and have it be the default behavior in the 
assembler.

Our support for it is to insert a NOP directly after an
instruction with a delayslot when in .set reorder mode.

Contributer: Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180584 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 23:31:35 +00:00
Reid Kleckner
4b55815303 [mc-coff] Forward Linker Option flags into the .drectve section
Summary:
This is modelled on the Mach-O linker options implementation and should
support a Clang implementation of #pragma comment(lib/linker).

Reviewers: rafael

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D724

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 19:34:41 +00:00
Rafael Espindola
93d0b06e2a Fix section relocation for SECTIONREL32 with immediate offset.
Patch by Kai Nacke. This matches the gnu as output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180568 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 19:27:05 +00:00
Akira Hatanaka
24b56e94f6 Test case for r180241.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180246 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 02:22:07 +00:00
Akira Hatanaka
4cc3d1b910 Test case for r180238.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180245 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25 02:21:09 +00:00
Jack Carter
a2b9d3d8ba Mips assembler: Add 64 bit testing for JAL
Contributer: Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24 21:52:42 +00:00
Chad Rosier
f74d82d8e4 Add test case for PR15779, which has previously been fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180058 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22 22:30:01 +00:00
Peter Collingbourne
4974b972e7 COFF: Fix weak external aliases.
Differential Revision: http://llvm-reviews.chandlerc.com/D700

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180034 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-22 18:48:56 +00:00
Akira Hatanaka
8d99ec5748 [mips] Fix InstAlias of XOR and OR macros. Set EmitAlias flag and change
operand type to uimm16.

Patch by Vladimir Medic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179872 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19 18:47:40 +00:00
Tim Northover
d3af696c08 ARM: Permit "sp" in ARM variant of STREXD instructions
Patch from Mihail Popa

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179854 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19 15:44:32 +00:00
Tim Northover
4521019c6f ARM: permit "sp" in ARM variants of MOVW/MOVT instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179847 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19 09:58:09 +00:00
Chad Rosier
3f1f9c3798 [ms-inline asm] Apply the condition code mnemonic aliases to both the Intel and
AT&T dialect.  Test case for r179804 as well.
rdar://13674398 and PR13340.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179813 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18 23:16:12 +00:00
Akira Hatanaka
26aef5b7d6 [mips] DSP-ASE move from HI/LO register instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179739 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18 00:52:44 +00:00
Peter Collingbourne
df39be6cb4 Add support for subsections to the ELF assembler. Fixes PR8717.
Differential Revision: http://llvm-reviews.chandlerc.com/D598

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179725 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-17 21:18:16 +00:00
Chad Rosier
d58f773b96 [ms-inline asm] Add support for the minus unary operator. Previously, we were
unable to handle cases such as __asm mov eax, 8*-8.

This patch also attempts to simplify the state machine.  Further, the error
reporting has been improved.  Test cases included, but more will be added to
the clang side shortly.
rdar://13668445


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179719 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-17 21:01:45 +00:00
Quentin Colombet
7c4cf030a8 Fix treatment of ARM unallocated hint instructions.
The reference manual defines only 5 permitted values for the immediate field of the "hint" instruction:
1. nop (imm == 0)
2. yield (imm == 1)
3. wfe (imm == 2)
4. wfi (imm == 3)
5. sev (imm == 4)

Therefore, restrict the permitted values for the "hint" instruction to 0 through 4.

Patch by Mihail Popa <Mihail.Popa@arm.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179707 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-17 18:46:12 +00:00
Jack Carter
8afc8b7e63 Mips assembler: Enable handling of nested expressions
This patch allows the Mips assembler to parse and emit nested 
expressions as instruction operands. It also extends the 
expansion of memory instructions when an offset is given as 
an expression. 

Contributer: Vladimir Medic



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179657 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-17 00:18:04 +00:00
Jim Grosbach
d0132ba722 ARM: Add VACLT and VACLE assembly aliases.
These are aliases for VACGT and VACGE, respectively, with the source
operands reversed.

rdar://13638090

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179575 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 22:42:50 +00:00
Jack Carter
b8145e3881 Mips assembler: Explicit floating point condition register recognition.
This patch allows the assembler to recognize $fcc0 
as a valid register for conditional move instructions. 

Corresponding test cases have been added.

Contributer: Vladimir Medic



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179567 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 22:21:55 +00:00
Nico Rieck
ef1762b6a1 Use object file specific section type for initial text section
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179494 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14 21:18:36 +00:00
Quentin Colombet
d64ee4455a ARM: Correct printing of pre-indexed operands.
According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes.
The MC disassembler was not obeying this when the offset is 0.
It was producing instructions like: str r0, [r1]!.
Correct syntax is: str r0, [r1, #0]!.

This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used.

Patch by Mihail Popa <Mihail.Popa@arm.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179398 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12 18:47:25 +00:00
Tim Northover
b6ad2bd511 AArch64: use full triple for ELF tests
These tests rely specifically on the names of ELF relocations, let alone any
other detail. There's no way they'd work if LLVM was emitting something else by
default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179376 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12 12:54:58 +00:00
Tim Northover
15e883787f AArch64: remove over-zealous use of CHECK-NEXT
It turns out some platforms (e.g. Windows) lay out their llvm-mc slightly
differently with extra newlines; there was no real reason for the test lines to
be consecutive, so this relaxes the FileCheck.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179375 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12 12:54:49 +00:00
Nico Rieck
f89da7210b Replace coff-/elf-dump with llvm-readobj
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179361 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12 04:06:46 +00:00
Michael Liao
02d2e61252 Add CLAC/STAC instruction encoding/decoding support
As these two instructions in AVX extension are privileged instructions for
special purpose, it's only expected to be used in inlined assembly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11 04:52:28 +00:00
Nico Rieck
18d49acdab MC: Support COFF image-relative MCSymbolRefs
Add support for the COFF relocation types IMAGE_REL_I386_DIR32NB and
IMAGE_REL_AMD64_ADDR32NB for 32- and 64-bit respectively. These are
similar to normal 4-byte relocations except that they do not include
the base address of the image.

Image-relative relocations are used for debug information (32-bit) and
SEH unwind tables (64-bit).

A new MCSymbolRef variant called 'VK_COFF_IMGREL32' is introduced to
specify such relocations. For AT&T assembly, this variant can be accessed
using the symbol suffix '@imgrel'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179240 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 23:28:17 +00:00
Kay Tiong Khoo
c92cc5d918 fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179223 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 21:52:25 +00:00
Peter Collingbourne
01a7b5c43e Use a scheme closer to that of GNU as when deciding the type of a
symbol with multiple .type declarations.

Differential Revision: http://llvm-reviews.chandlerc.com/D607

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179184 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 16:52:15 +00:00
Tim Northover
8c9e52a9fc ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.
These instructions aren't universally available, but depend on a specific
extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new
feature is appropriate.

This also enables the feature by default on A-class cores which usually have
these extensions, to avoid breaking existing code and act as a sensible
default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179171 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 12:08:35 +00:00
Chad Rosier
e112453fc3 [ms-inline asm] Add support for numeric displacement expressions in bracketed
memory operands.

Essentially, this layers an infix calculator on top of the parsing state
machine.  The scale on the index register is still expected to be an immediate

 __asm mov eax, [eax + ebx*4]

and will not work with more complex expressions.  For example,

 __asm mov eax, [eax + ebx*(2*2)]

The plus and minus binary operators assume the numeric value of a register is
zero so as to not change the displacement.  Register operands should never
be an operand for a multiply or divide operation; the scale*indexreg
expression is always replaced with a zero on the operand stack to prevent
such a case.
rdar://13521380


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178881 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05 16:28:55 +00:00
Richard Osborne
e50faa754b [XCore] Add bru instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178783 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04 20:05:35 +00:00
Richard Osborne
c6ff29713d [XCore] The RRegs register class is a superset of GRRegs.
At the time when the XCore backend was added there were some issues with
with overlapping register classes but these all seem to be fixed now.
Describing the register classes correctly allow us to get rid of a
codegen only instruction (LDAWSP_lru6_RRegs) and it means we can
disassemble ru6 instructions that use registers above r11.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04 19:57:46 +00:00
Rafael Espindola
d787a41b11 Implement the "mips endian" for r_info.
Normally r_info is just a 32 of 64 bit number matching the endian of the rest
of the file. Unfortunately, mips 64 bit little endian is special: The top 32
bits are a little endian number and the following 32 are a big endian one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178694 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03 21:02:51 +00:00
Richard Osborne
6107bbbbdf [XCore] Check disassembly of the st8 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178689 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03 20:07:11 +00:00
Richard Osborne
ef6343347a [XCore] Update disassembler test to improve coverage of the instructions.
Previously some instructions were unintentionally covered twice and
others were not covered at all.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178688 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03 20:07:06 +00:00
Eric Christopher
76e70f340c Implements low-level object file format specific output for COFF and
ELF with support for:

- File headers
- Section headers + data
- Relocations
- Symbols
- Unwind data (only COFF/Win64)

The output format follows a few rules:
- Values are almost always output one per line (as elf-dump/coff-dump already do). - Many values are translated to something readable (like enum names), with the raw value in parentheses.
- Hex numbers are output in uppercase, prefixed with "0x".
- Flags are sorted alphabetically.
- Lists and groups are always delimited.

Example output:
---------- snip ----------
Sections [
  Section {
    Index: 1
    Name: .text (5)
    Type: SHT_PROGBITS (0x1)
    Flags [ (0x6)
      SHF_ALLOC (0x2)
      SHF_EXECINSTR (0x4)
    ]
    Address: 0x0
    Offset: 0x40
    Size: 33
    Link: 0
    Info: 0
    AddressAlignment: 16
    EntrySize: 0
    Relocations [
      0x6 R_386_32 .rodata.str1.1 0x0
      0xB R_386_PC32 puts 0x0
      0x12 R_386_32 .rodata.str1.1 0x0
      0x17 R_386_PC32 puts 0x0
    ]
    SectionData (
      0000: 83EC04C7 04240000 0000E8FC FFFFFFC7  |.....$..........|
      0010: 04240600 0000E8FC FFFFFF31 C083C404  |.$.........1....|
      0020: C3                                   |.|
    )
  }
]
---------- snip ----------

Relocations and symbols can be output standalone or together with the section header as displayed in the example.
This feature set supports all tests in test/MC/COFF and test/MC/ELF (and I suspect all additional tests using elf-dump), making elf-dump and coff-dump deprecated.

Patch by Nico Rieck!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178679 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03 18:31:38 +00:00
Tim Northover
4385f5dfce AArch64: implement ETMv4 trace system registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178637 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03 12:31:29 +00:00
Rafael Espindola
04011e8429 Fix the fde encoding used by mips to match gas.
This finally fixes the encoding. The patch also
* Removes eh-frame.ll. It was an unnecessary .ll to .o test that was checking
  the wrong value.
* Merge fde-reloc.s and eh-frame.s into a single test, since the only difference
  was the run lines.
* Don't blindly test the content of the entire .eh_frame section. It makes it
  hard to anyone actually fixing a bug and hitting a difference in a binary
  blob. Instead, use a CHECK for each field and document what is being checked.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178615 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03 03:13:19 +00:00
Jack Carter
732f4bc7c4 Mips direct object exception handling regression
Revision 177141 caused a regression in all but
mips64 little endian. That is because none of the
other Mips targets had test cases checking the 
contents of the .eh_frame section. This patch fixes
both the llvm code and adds an assembler test case 
to include the current 4 flavors.

The test cases unfortunately rely on llvm-objdump. A
preferable method would be to use a pretty printer output
such as what readelf -wf <elf_file> would give.

I also changed the name of the test case to correct a typo.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178506 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01 21:55:15 +00:00
Jack Carter
af7da5cb99 [Mips Assembler] Add support for OR macro with imediate opperand
Mips assembler supports macros that allows the OR instruction 
to have an immediate parameter. This patch adds an instruction 
alias that converts this macro into a Mips ORI instruction. 

Contributer: Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178316 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 23:45:13 +00:00
Michael Liao
c26392aa5d Add support of RDSEED defined in AVX2 extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178314 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 23:41:26 +00:00
Jack Carter
94fcfaf3a9 [Mips Assembler] Add alias definitions for jal
Mips assembler allows following to be used as aliased instructions:
jal $rs for jalr $rs
jal $rd,$rd for jalr $rd,$rs

This patch provides alias definitions in td files and test cases to show the usage.

Contributer: Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178304 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 23:02:21 +00:00
Gordon Keiser
ce88835110 Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when the upper bit is set.
They should always be zero-extended, not sign extended.  Added test case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178275 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 19:22:28 +00:00
Rafael Espindola
30509ee8a3 Move test since it depends on the X86 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178249 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 17:01:28 +00:00
Tim Northover
42a1b2f0b1 AArch64: implement GICv3 system registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178236 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 14:30:46 +00:00
Michael Gottesman
21fb0193b2 Revert "Updated ELF relocation test for .eh_frame section"
This reverts commit c8d6536422.

This broke a bunch of the buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178222 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 05:14:26 +00:00
Jack Carter
c8d6536422 Updated ELF relocation test for .eh_frame section
Made sure we were looking a correct section
Added Mips32/64 as an extra check
Updated llvm-objdump to generate symbolic info for Mips relocations


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178190 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27 22:58:49 +00:00
Chad Rosier
dd40e8cd54 [ms-inline asm] Add support of imm displacement before bracketed memory
expression.  Specifically, this syntax:

 ImmDisp [ BaseReg + Scale*IndexReg + Disp ] 

We don't currently support:

 ImmDisp [ Symbol ]

rdar://13518671


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178186 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27 21:49:56 +00:00
Jack Carter
09d27fb6ab test file name change to correct typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178174 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27 20:07:48 +00:00