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15637 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
3e60a232c1 Revert this for now, PUNPCKLDQ dont operate on v4f32 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112090 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-25 21:26:37 +00:00
Daniel Dunbar
3d6e4c3111 X86: Fix misencode of RI64mi8. This fixes OpenSSL / x86_64-apple-darwin10 / clang -O3. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112089 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-25 21:11:02 +00:00
Jim Grosbach
f78ee6316b Don't override the var from the enclosing scope. 
When doing copy/paste/modify, it's apparently rather important to remember
the 'modify' bit...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112075 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-25 19:11:34 +00:00
Chris Lattner
574aab5700 zap dead code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112073 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-25 19:00:00 +00:00
Benjamin Kramer
fc19695c9a Remove dead recursive function. Yay for clang -Wunused-function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112060 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-25 17:27:58 +00:00
Daniel Dunbar
3cc3283fcb ARM/Thumb2: Fix a misselect in getARMCmp, when attempting to adjust a signed 
comparison that would overflow.
 - The other under/overflow cases can't actually happen because the immediates
   which would trigger them are legal (so we don't enter this code), but
   adjusted the style to make it clear the transform is always valid.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112053 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-25 16:58:05 +00:00
Eric Christopher
61c3f9ae06 Do type checks before we bother to do everything else. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112039 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-25 08:43:57 +00:00
Anton Korobeynikov
9f7f83b861 Fix nasty mingw32 bug, which e.g. prevented llvm-gcc bootstrap there. 
Mark _alloca call as clobberring EFLAGS, otherwise some DCE might remove
other flags-clobberring stuff (e.g. cmp instructions) occuring after
_alloca call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112034 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-25 07:50:11 +00:00
Eric Christopher
b1cc848d1a Reorganize load mechanisms. Handle types in a little less fixed way. 
Fix some todos.  No functional change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112031 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-25 07:23:49 +00:00
Bruno Cardoso Lopes
f76c55aa40 PUNPCKLDQ should also be used for v4f32 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112020 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-25 02:55:40 +00:00
Bruno Cardoso Lopes
7338bbd32a teach lowering to get target specific nodes for pshufd, emulating the same isel behavior for now, so we can pass all vector shuffle tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112017 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-25 02:35:37 +00:00
Eric Christopher
992ea38e0e Fix predicate and add a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111981 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 22:34:11 +00:00
Eric Christopher
e24d66f525 Rework braindead conditionals I put in yesterday. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111974 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 22:07:27 +00:00
Eric Christopher
9f782d4dcf Fix thumb2 mode loads to have the correct operand ordering. Add a todo 
to fix this in the port.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111973 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 22:03:02 +00:00
Jim Grosbach
3197380143 Add ARM heuristic for when to allocate a virtual base register for stack 
access. rdar://8277890&7352504

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111968 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 21:19:33 +00:00
Daniel Dunbar
fba88d49e3 MC/X86: Tweak imul recognition, previous hack only applies for the imul form 
taking immediates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111950 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 19:37:56 +00:00
Daniel Dunbar
ae528f65ba MC/X86: Add custom hack for recognizing "imul $12, %eax" and friends. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111947 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 19:24:18 +00:00
Daniel Dunbar
ee9102587e MC/X86: Warn on scale factors > 1 without index register, instead of erroring, 
for 'as' compatibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111945 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 19:13:38 +00:00
Jim Grosbach
a273442891 Move enabling the local stack allocation pass into the target where it belongs. 
For now it's still a command line option, but the interface to the generic
code doesn't need to know that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111942 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 19:05:43 +00:00
Jim Grosbach
cd59dc5e81 add ARM cmd line option to force always using virtual base regs when possible. 
Intended to help ease reproducing problems by increasing base register usage
after heuristics for only using the when needed are in place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111930 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 18:04:52 +00:00
Dan Gohman
92b651fb19 Fix X86's isLegalAddressingMode to recognize that static addresses 
need not be RIP-relative in small mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111917 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 15:55:12 +00:00
Kalle Raiskila
55aebef654 Fix SPU BE to use all the available return registers. 
llc used to assert on the added testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111911 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 11:50:48 +00:00
Kalle Raiskila
f53fdc2e45 Remove some dead code from SPU BE that remained 
from 64bit vector support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111910 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 11:05:51 +00:00
Bruno Cardoso Lopes
8878e21fe6 Use pshufhw and pshuflw in more cases and fix getTargetShuffleNode number of arguments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111890 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 01:16:15 +00:00
Bill Wendling
5e7044bd0e Add comments for what the condition code symbols mean. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111889 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 01:11:30 +00:00
Eric Christopher
882d62e2db Update comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111887 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 01:10:52 +00:00
Eric Christopher
2012c7bb7b Fix the opcode and the operands for the load instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111885 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 01:10:04 +00:00
Eric Christopher
f06f309002 Add register class hack that needs to go away, but makes it more obvious 
that it needs to go away.  Use loadRegFromStackSlot where possible.

Also, remember to update the value map.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111883 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 00:50:47 +00:00
Eric Christopher
cb0b04ba6f Add some more debugging code, make it more obvious that RegOffset is 
getting an address for an object and select some default values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111871 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-24 00:07:24 +00:00
Eric Christopher
1dfb4d31e0 Don't need the extra register here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111864 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 23:28:04 +00:00
Eric Christopher
8654c71e56 Add some more "get address into register" code and a more TODOs/FIXMEs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111860 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 23:14:31 +00:00
Eric Christopher
7fe55b739c Add an ARMFunctionInfo member and use it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111854 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 22:32:45 +00:00
Eric Christopher
8300712c1e Start getting ARM loads/address computation going. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111850 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 21:44:12 +00:00
Bruno Cardoso Lopes
3efc0778c9 Start using target speficic nodes for shuffles: pshufhw and pshuflw 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111837 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 20:41:02 +00:00
Gabor Greif
11bc1652c9 tyops 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111835 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 20:30:51 +00:00
Chris Lattner
d80c7e1232 Add a new llvm.x86.int intrinsic, allowing access to the 
x86 int and int3 instructions.  Patch by Peter Housel!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111831 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 19:39:25 +00:00
Chris Lattner
b7f243a638 random improvement for variable shift codegen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111813 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 17:30:29 +00:00
Anton Korobeynikov
4654a07e25 Revert invalid r111792. Jump tables are not broken on x86-64 / coff, 
it's COFF emitter which does not support differences of two symbols
(and needs to be fixed). GAS is pretty fine with code produced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111801 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 07:38:51 +00:00
Michael J. Spencer
3464cec4d8 Workaround broken jump tables on x86-64 COFF. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111792 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-23 04:45:37 +00:00
Anton Korobeynikov
699647cabc Use rip-rel addressing on win64 by default. For this we just 
defaults to small pic code model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111741 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-21 17:21:11 +00:00
Michael J. Spencer
da0bfcdaf9 MC: Add partial x86-64 support to COFF. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111728 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-21 05:58:13 +00:00
Dan Gohman
8bef744518 Fix x86 fast-isel's cmp+branch folding to avoid folding when the 
comparison is in a different basic block from the branch. In such
cases, the comparison's operands may not have initialized virtual
registers available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111709 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-21 02:32:36 +00:00
Bruno Cardoso Lopes
bf8154a439 Prepare LowerVECTOR_SHUFFLEv8i16 to use x86 target specific nodes directly 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111704 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-21 01:32:18 +00:00
Bruno Cardoso Lopes
3157ef1c13 This is the first step towards refactoring the x86 vector shuffle code. The 
general idea here is to have a group of x86 target specific nodes which are
going to be selected during lowering and then directly matched in isel.

The commit includes the addition of those specific nodes and a *bunch* of
patterns, and incrementally we're going to switch between them and what we
have right now. Both the patterns and target specific nodes can change as
we move forward with this work.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111691 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-20 22:55:05 +00:00
Bill Wendling
55ae515f9d Create the new linker type "linker_private_weak_def_auto". 
It's similar to "linker_private_weak", but it's known that the address of the
object is not taken. For instance, functions that had an inline definition, but
the compiler decided not to inline it. Note, unlike linker_private and
linker_private_weak, linker_private_weak_def_auto may have only default
visibility.  The symbols are removed by the linker from the final linked image
(executable or dynamic library).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111684 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-20 22:05:50 +00:00
Bob Wilson
b31a11b466 Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend and 
zero-extend operations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111614 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-20 04:54:02 +00:00
Eric Christopher
f762fbe4fa Fix loop conditionals (MO.isDef() asserts that it's a reg) and 
move some constraints around.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111594 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-20 00:36:24 +00:00
Eric Christopher
cb59229a4a Add a couple of random comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111592 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-20 00:20:31 +00:00
Jim Grosbach
e2f556933e Better handling of offsets on frame index references. rdar://8277890 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111585 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 23:52:25 +00:00
Jim Grosbach
74d7b0af58 Add Thumb1 support for virtual frame indices. 
rdar://8277890



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111533 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 17:52:13 +00:00