Commit Graph

21722 Commits

Author SHA1 Message Date
Daniel Sanders
8dc7f94f4d [mips][msa] Float vector constants cannot use ldi.[wd] directly. Bitcast from the appropriate integer vector type.
Fixes an instruction selection failure detected by llvm-stress.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195444 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-22 11:24:50 +00:00
Kostya Serebryany
a7e8d6581f Revert r195318 as it causes miscompilation (PR18029)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195439 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-22 10:30:39 +00:00
Hao Liu
e74a644b38 Fix the bugs about AArch64 Load/Store vector types and bitcast between i64 and vector types.
e.g. "%tmp = load <2 x i64>* %ptr" can't be selected. 
     "%tmp = bitcast i64 %in to <2 x i32>" can't be selected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195424 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-22 08:47:22 +00:00
Jiangning Liu
0282fe6d91 For AArch64 back-end instruction selection, lower Neon_Lowxxx with EXTRCT_SUBREG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195408 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-22 02:45:13 +00:00
NAKAMURA Takumi
ca3c03a167 Tweak 3 tests in llvm/test/CodeGen/X86 to add -mcpu=generic since r195383.
They failed on bdver2 buildslave.

FIXME: FileCheck-ize them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195407 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-22 02:28:04 +00:00
Yi Jiang
709a31b5f9 SLP Vectorizer: Extract cost will only be added once even if the scalar has multiple external uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195406 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-22 01:57:02 +00:00
Tom Stellard
0ffcaa0d54 SelectionDAG: Optimize expansion of vec_type = BITCAST scalar_type
The legalizer can now do this type of expansion for more
type combinations without loading and storing to and
from the stack.

NOTE: This is a candidate for the 3.4 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195398 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-22 00:41:05 +00:00
Eric Christopher
2d5d104c5b In Dwarf 3 (and Dwarf 2) attributes whose value are offsets into a
section use the form DW_FORM_data4 whilst in Dwarf 4 and later they
use the form DW_FORM_sec_offset.

This patch updates the places where such attributes are generated to
use the appropriate form depending on the Dwarf version. The DIE entries
affected have the following tags:
DW_AT_stmt_list, DW_AT_ranges, DW_AT_location, DW_AT_GNU_pubnames,
DW_AT_GNU_pubtypes, DW_AT_GNU_addr_base, DW_AT_GNU_ranges_base

It also adds a hidden command line option "--dwarf-version=<uint>"
to llc which allows the version of Dwarf to be generated to override
what is specified in the metadata; this makes it possible to update
existing tests to check the debugging information generated for both
Dwarf 4 (the default) and Dwarf 3 using the same metadata.

Patch (slightly modified) by Keith Walker!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195391 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 23:46:41 +00:00
Ekaterina Romanova
46f7257ed1 SHLD/SHRD are VectorPath (microcode) instructions known to have poor latency on certain architectures. While generating SHLD/SHRD instructions is acceptable when optimizing for size, optimizing for speed on these platforms should be implemented using alternative sequences of instructions composed of add, adc, shr, shl, or and lea which are directPath instructions. These alternative instructions not only have a lower latency but they also increase the decode bandwidth by allowing simultaneous decoding of a third directPath instruction.
AMD's processors family K7, K8, K10, K12, K15 and K16 are known to have SHLD/SHRD instructions with very poor latency. Optimization guides for these processors recommend using an alternative sequence of instructions. For these AMD's processors, I disabled folding (or (x << c) | (y >> (64 - c))) when we are not optimizing for size.

It might be beneficial to disable this folding for some of the Intel's processors. However, since I couldn't find specific recommendations regarding using SHLD/SHRD instructions on Intel's processors, I haven't disabled this peephole for Intel.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195383 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 23:21:26 +00:00
Peter Collingbourne
934d1f83ae Introduce two command-line flags for the instrumentation pass to control whether the labels of pointers should be ignored in load and store instructions
The new command line flags are -dfsan-ignore-pointer-label-on-store and -dfsan-ignore-pointer-label-on-load. Their default value matches the current labelling scheme.

Additionally, the function __dfsan_union_load is marked as readonly.

Patch by Lorenzo Martignoni!

Differential Revision: http://llvm-reviews.chandlerc.com/D2187

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195382 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 23:20:54 +00:00
Artyom Skrobov
bf73d8f1f2 [ARM] add the overlooked tests for Cortex-A7 build attributes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195365 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 16:22:39 +00:00
Daniel Sanders
959f0c3f44 [mips][msa] Fix a corner case in performORCombine() when combining nodes into VSELECT.
Mask == ~InvMask asserts if the width of Mask and InvMask differ.
The combine isn't valid (with two exceptions, see below) if the widths differ
so test for this before testing Mask == ~InvMask.

In the specific cases of Mask=~0 and InvMask=0, as well as Mask=0 and
InvMask=~0, the combine is still valid. However, there are more appropriate
combines that could be used in these cases such as folding x & 0 to 0, or
x & ~0 to x.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195364 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 16:11:31 +00:00
Daniel Sanders
f89ddfccc0 Add support for legalizing SETNE/SETEQ by inverting the condition code and the result of the comparison.
Summary:
LegalizeSetCCCondCode can now legalize SETEQ and SETNE by returning the inverse
condition and requesting that the caller invert the result of the condition.

The caller of LegalizeSetCCCondCode must handle the inverted CC, and they do
so as follows:
  SETCC, BR_CC:
    Invert the result of the SETCC with SelectionDAG::getNOT()
  SELECT_CC:
    Swap the true/false operands.

This is necessary for MSA which lacks an integer SETNE instruction.

Reviewers: resistor

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2229

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195355 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 13:24:49 +00:00
Evgeniy Stepanov
52658c9db5 [msan] Propagate condition origin in select instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195349 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 12:00:24 +00:00
Daniel Sanders
001a93bbcb [mips][msa/dsp] Only do DSP combines if DSP is enabled.
Fixes a crash (null pointer dereferenced) when MSA is enabled.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195343 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 11:40:14 +00:00
Evgeniy Stepanov
ae89383daa Use multiple filecheck prefixes in msan instrumentation tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195342 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 11:37:16 +00:00
NAKAMURA Takumi
b05bddb4ba Revert r195317 (and r195333), "Teach ISel not to optimize 'optnone' functions."
It broke, at least, i686 target. It is reproducible with "llc -mtriple=i686-unknown".

FYI, it didn't appear to add either "-O0" or "-fast-isel".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195339 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 10:55:15 +00:00
Kostya Serebryany
12f0390618 add 'REQUIRES: asserts' to a test that uses 'llc -debug'; this fixes the no-asserts build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195333 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 09:28:16 +00:00
Ana Pazos
6345249972 Implemented Neon scalar vdup_lane intrinsics.
Fixed scalar dup alias and added test case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195330 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 08:16:15 +00:00
Ana Pazos
1c93766aa5 Implemented Neon scalar by element intrinsics.
Intrinsics implemented: vqdmull_lane, vqdmulh_lane, vqrdmulh_lane,
vqdmlal_lane, vqdmlsl_lane scalar Neon intrinsics.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195327 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 07:37:04 +00:00
Kostya Serebryany
42a9da35b8 Don't speculate loads under ThreadSanitizer
Summary:
Don't speculate loads under ThreadSanitizer.
This fixes https://code.google.com/p/thread-sanitizer/issues/detail?id=40
Also discussed here: http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-November/067929.html

Reviewers: chandlerc

Reviewed By: chandlerc

CC: llvm-commits, dvyukov

Differential Revision: http://llvm-reviews.chandlerc.com/D2227

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195324 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 07:29:28 +00:00
Bill Wendling
072ebe59e2 The basic problem is that some mainstream programs cannot deal with the way
clang optimizes tail calls, as in this example:

int foo(void);
int bar(void) {
 return foo();
}

where the call is transformed to:

  calll .L0$pb
.L0$pb:
  popl  %eax
.Ltmp0:
  addl  $_GLOBAL_OFFSET_TABLE_+(.Ltmp0-.L0$pb), %eax
  movl  foo@GOT(%eax), %eax
  popl  %ebp
  jmpl  *%eax                   # TAILCALL

However, the GOT references must all be resolved at dlopen() time, and so this
approach cannot be used with lazy dynamic linking (e.g. using RTLD_LAZY), which
usually populates the PLT with stubs that perform the actual resolving.

This patch changes X86TargetLowering::LowerCall() to skip tail call
optimization, if the called function is a global or external symbol.

Patch by Dimitry Andric!

PR15086

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195318 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 07:04:30 +00:00
Paul Robinson
6079f00035 Teach ISel not to optimize 'optnone' functions.
Based on work by Andrea Di Biagio.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195317 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 06:33:32 +00:00
Reed Kotler
ce10f18555 Add, to constant islands, long jumps similar to ARM far branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195312 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-21 05:13:23 +00:00
Hal Finkel
1e81642366 PPC popcnt[dw] do not have record forms
The instruction definitions incorrectly specified that popcntd and popcntw have
record forms; they do not. This mistake was causing invalid code generation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195272 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-20 20:54:55 +00:00
Benjamin Kramer
16e2f0ef1a MachineBlockPlacement: Strengthen the source order bias when picking an exit block.
We now only allow breaking source order if the exit block frequency is
significantly higher than the other exit block. The actual bias is
currently under a flag so the best cut-off can be found; the flag
defaults to the old behavior. The idea is to get some benchmark coverage
over different values for the flag and pick the best one.

When we require the new frequency to be at least 20% higher than the old
frequency I see a 5% speedup on zlib's deflate when compressing a random
file on x86_64/westmere. Hal reported a small speedup on Fhourstones on
a BG/Q and no regressions in the test suite.

The test case is the full long_match function from zlib's deflate. I was
reluctant to add it for previous tweaks to branch probabilities because
it's large and potentially fragile, but changed my mind since it's an
important use case and more likely to break with all the current work
going into the PGO infrastructure.

Differential Revision: http://llvm-reviews.chandlerc.com/D2202

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195265 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-20 19:08:44 +00:00
Daniel Sanders
e4e260e6a7 FileCheck: fix a bug with multiple --check-prefix options. Similar to r194565
Summary:
Directives are being ignored, when they occur between a partial-word false
match and any match on another prefix.

For example, with FOO and BAR prefixes:
   _FOO
   FOO: foo
   BAR: bar
FileCheck incorrectly matches:
   fog
   bar

This happens because FOO falsely matched as a partial word at '_FOO' and was
ignored while BAR matched at 'BAR:'. The match of BAR is incorrectly returned
as the 'first match' causing the FOO directive to be discarded.

Fixed this the same way as r194565 (D2166) did for a similar test case.
The partial-word false match should be counted as a match for the purposes of
finding the first match of a prefix, but should be returned as a false match
using CheckTy::CheckNone so that it isn't treated as a directive.

Fixes PR17995

Reviewers: samsonov, arsenm

Reviewed By: samsonov

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2228

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195248 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-20 13:25:05 +00:00
Elena Demikhovsky
5cd32afac4 AVX-512: Concat 4 128-bit vectors in one 512-bit vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-20 09:10:40 +00:00
Yuchen Wu
d23c759c0f llvm-cov: Added file checksum to gcno and gcda files.
Instead of permanently outputting "MVLL" as the file checksum, clang
will create gcno and gcda checksums by hashing the destination block
numbers of every arc. This allows for llvm-cov to check if the two gcov
files are synchronized.

Regenerated the test files so they contain the checksum. Also added
negative test to ensure error when the checksums don't match.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195191 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-20 04:15:05 +00:00
Hal Finkel
eda8f6708d PPC: Optimize rldicl generation for masked shifts
Masking operations (where only some number of the low bits are being kept) are
selected to rldicl(x, 0, mb). If x is a logical right shift (which would become
rldicl(y, 64-n, n)), we might be able to fold the two instructions together:

  rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb) for n <= mb

The right shift is really a left rotate followed by a mask, and if the explicit
mask is a more-restrictive sub-mask of the mask implied by the shift, only one
rldicl is needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195185 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-20 01:10:15 +00:00
David Blaikie
6fe6dc19f8 DebugInfo: Partial implementation of DWARF type units.
Emit DW_TAG_type_units into the debug_info section using compile unit
headers. This is bogus/unusable by debuggers, but testable and provides
more isolated review.

Subsequent patches will include support for type unit headers and
emission into the debug_types section, as well as comdat grouping the
types based on their hash. Also the CompileUnit type will be renamed
'Unit' and relevant portions pulled out into respective CompileUnit and
TypeUnit types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195166 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 23:08:21 +00:00
Arnold Schwaighofer
4bc2e3a32d SLPVectorizer: Fix stale for Value pointer array
We are slicing an array of Value pointers and process those slices in a loop.
The problem is that we might invalidate a later slice by vectorizing a former
slice.

Use a WeakVH to track the pointer. If the pointer is deleted or RAUW'ed we can
tell.

The test case will only fail when running with libgmalloc.

radar://15498655

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195162 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 22:20:20 +00:00
Petar Jovanovic
2fb0234d5f [mips] Resolve relocation for the stubs in MCJIT when load address is known
Instead of processing relocation for branch to stubs right away, emit a
modified relocation and add it to queue to be resolved later when final load
address is known.
This resolves seven MIPS MCJIT issues that were caused by missing relocation
fixups at the end.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195157 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 21:56:00 +00:00
Rafael Espindola
edeaa6454e Make it explicit that nulls are not allowed in names.
The object files we support use null terminated strings, so there is no way to
support these.

This patch adds an assert to catch bad API use and an error check in the .ll
parser.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195155 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 21:12:39 +00:00
Jack Carter
0233715d74 reverts 195057 per request
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195152 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 20:53:28 +00:00
Rafael Espindola
72935dd909 Support multiple COFF sections with the same name but different COMDAT.
This is the first step to fix pr17918.

It extends the .section directive a bit, inspired by what the ELF one looks
like. The problem with using linkonce is that given

.section foo
.linkonce....

.section foo
.linkonce

we would already have switched sections when getting to .linkonce. The cleanest
solution seems to be to add the comdat information in the .section itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195148 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 19:52:52 +00:00
Cameron McInally
c5a925c198 Fix assembly operands for the SSE2 cvtsd2ss instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195129 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 14:36:00 +00:00
Simon Atanasyan
c5e99819f4 [Mips] Adjust float ABI settings in case of MIPS16 mode.
Hard float for mips16 means essentially to compile as soft float but to
use a runtime library for soft float that is written with native mips32
floating point instructions (those runtime routines run in mips32 hard
float mode).

The patch reviewed by Reed Kotler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 12:20:17 +00:00
Chandler Carruth
ed1951e79f Fix an issue where SROA computed different results based on the relative
order of slices of the alloca which have exactly the same size and other
properties. This was found by a perniciously unstable sort
implementation used to flush out buggy uses of the algorithm.

The fundamental idea is that findCommonType should return the best
common type it can find across all of the slices in the range. There
were two bugs here previously:

1) We would accept an integer type smaller than a byte-width multiple,
   and if there were different bit-width integer types, we would accept
   the first one. This caused an actual failure in the testcase updated
   here when the sort order changed.
2) If we found a bad combination of types or a non-load, non-store use
   before an integer typed load or store we would bail, but if we found
   the integere typed load or store, we would use it. The correct
   behavior is to always use an integer typed operation which covers the
   partition if one exists.

While a clever debugging sort algorithm found problem #1 in our existing
test cases, I have no useful test case ideas for #2. I spotted in by
inspection when looking at this code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195118 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 09:03:18 +00:00
Daniel Jasper
f5afe719df Add .clang-format without column limit to subdirectory tests/.
A column limit in the test folder can lead to trouble as the RUN, CHECK,
etc. comments can potentially be broken over multiple lines changing
their meaning. Without column limit, clang-format will simply keep the
test author's line breaks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195100 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 04:26:05 +00:00
Andrew Trick
d73d4f4ef2 Use symbolic operands in the patchpoint folding routine and fix a spilling bug.
Fixes <rdar://15487687> [JS] AnyRegCC argument ends up being spilled

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195094 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 03:29:59 +00:00
Hao Liu
36c7806f4e Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195078 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 02:17:05 +00:00
Jiangning Liu
f11b55c5cc Implement AArch64 SISD intrinsics for vget_high and vget_low.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195074 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 01:46:48 +00:00
Kevin Qin
282a979ddd implement MC layer of AArch64 neon instruction PMULL and PMULL2 with 128 bit integer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195072 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 01:40:25 +00:00
Jiangning Liu
01dd5728cc Add predicate for AArch64 crypto instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195071 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 01:38:31 +00:00
Jack Carter
e53969b475 [Mips] Support for MicroMips STO refactoring.
No true functional changes.

Change the "hack" name of emitMipsHackSTOCG to emitSymSTO.

Remove demonstration code in AsmParser for emitMipsHackSTOCG and
emitMipsHackELFFlags. The STO field is in an ELF symbol and is not
an explicit directive. That said, we are missing the compliment call
in AsmParser and that will need to be addressed soon.

XFAIL dummy tests for emitMipsHackELFFlags and emitMipsHackELFFlags.
These will built out with following patches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195067 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 01:25:18 +00:00
David Blaikie
26efdc5621 llvm-dwarfdump: support for emitting only the debug_types section using -debug-dump
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195063 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 00:29:42 +00:00
Reid Kleckner
a7b7a7d629 Revert "COFF: Emit all MCSymbols rather than filtering out some of them"
This reverts commit r190888, to fix PR17967.  The original change wasn't
the right way to get @feat.00 into the object file.  The right fix is to
make @feat.00 be a global symbol.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195053 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 23:08:12 +00:00
Adrian Prantl
940267e7f2 Debug info: Let LowerDbgDeclare perfom the dbg.declare -> dbg.value
lowering only for load/stores to scalar allocas. The resulting values
confuse the backend and don't add anything because we can describe
array-allocas with a dbg.declare intrinsic just fine.

rdar://problem/15464571

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195052 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 23:04:38 +00:00
Paul Robinson
fe45fd084d The 'optnone' attribute means don't inline anything into this function
(except functions marked always_inline).
Functions with 'optnone' must also have 'noinline' so they don't get
inlined into any other function.

Based on work by Andrea Di Biagio.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195046 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 21:44:03 +00:00