Commit Graph

21722 Commits

Author SHA1 Message Date
Sebastian Pop
5230ad61fd delinearization of arrays
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194527 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 22:47:20 +00:00
Nadav Rotem
6c84f7ad2d Fold (iszero(A&K1) | iszero(A&K2)) -> (A&(K1|K2)) != (K1|K2) if we know that K1 and K2 are 'one-hot' (only one bit is on).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194525 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 22:38:59 +00:00
Nadav Rotem
f3bd3ea3fe FoldBranchToCommonDest merges branches into a single branch with or/and of the condition. It has a heuristics for estimating when some of the dependencies are processed by out-of-order processors. This patch adds another rule to the heuristics that says that if the "BonusInstruction" that we speculatively execute is used by the condition of the second branch then it is okay to hoist it. This change exposes more opportunities for other passes to transform the code. It does not matter that much that we if-convert the code because the selectiondag builder splits or/and branches into multiple branches when profitable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 22:37:16 +00:00
Akira Hatanaka
714e04b84a [mips] Fix a bug in function CC_MipsO32_FP64. The second double precision
argument was not being passed in $f14.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194522 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 22:16:18 +00:00
Akira Hatanaka
fe438bba94 [mips] Run test case with command line option -mattr=+fp64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194519 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 22:06:45 +00:00
Justin Bogner
dc6b4b4fc2 Protect user-supplied runtime library functions in LTO
Add user-supplied C runtime and compiler-rt library functions to
llvm.compiler.used to protect them from premature optimization by
passes like -globalopt and -ipsccp.  Calls to (seemingly unused)
runtime library functions can be added by -instcombine and instruction
lowering.

Patch by Duncan Exon Smith, thanks!

Fixes <rdar://problem/14740087>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194514 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 21:44:01 +00:00
Tim Northover
59e648e3c8 ARM: diagnose invalid system LDM/STM
The system LDM and STM instructions can't usually writeback to the base
register. The one exception is when an LDM is actually an exception-return
(i.e. contains PC in the register list).

(There's already a test that "ldm sp!, {r0-r3, pc}^" works, which is why there
is no positive test).

rdar://problem/15223374

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194512 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 21:32:41 +00:00
Akira Hatanaka
0a227ad4d5 [mips] Fix and re-enable a test case that has been disabled for a long time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194510 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 21:03:57 +00:00
Peter Zotov
1ba15ab134 [OCaml] Dynamically link LLVM on --enable-shared builds
This commit significantly speeds up both bytecode and native
builds of LLVM clients (from ~20 second to sub-second link time),
and allows to invoke LLVM functions from OCaml toplevel.

The behavior for --disable-shared builds is unchanged.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194509 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 20:55:49 +00:00
Rafael Espindola
46456f6a2f Corruptly merge constants with explicit and implicit alignments.
Constant merge can merge a constant with implicit alignment with one that has
explicit alignment. Before this change it was assuming that the explicit
alignment was higher than the implicit one, causing the result to be under
aligned in some cases.

Fixes pr17815.

Patch by Chris Smowton!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194506 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 20:21:43 +00:00
Chad Rosier
13c83a2a09 [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar
copy in MC layer. Added the MC layer tests.  Fixed triple setting in test cases.

Patch by Ana Pazos <apazos@codeaurora.org>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194501 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 19:13:08 +00:00
Andrew Trick
0085d5e5ae Simplify operand folding when rematerializing a load.
We already know how to fold a reload from a frameindex without
analyzing the load instruction. Generalize this to handle any
frameindex load. This streamlines the logic for rematerializing loads
from stack arguments. As a side effect, it allows stackmaps to record
a stack argument location without spilling it.

Verified no effect on codegen for llvm test-suite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194497 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 18:06:12 +00:00
Daniel Sanders
9e2838e29b [mips][msa] Enable inlinse assembly for MSA.
Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier:
  asm ("ldi.w %w0, 1", "=f"(result));

Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended
output. This is a consequence of differences in the internal handling of
the registers in each compiler. To be source-compatible between the
compilers, users must use the 'w' print-modifier.

MSA registers (including control registers) are supported in clobber lists.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194476 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 12:56:01 +00:00
Benjamin Kramer
f681437cb0 SimplifyCFG: Use existing constant folding logic when forming switch tables.
Both simpler and more powerful than the hand-rolled folding logic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194475 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 12:24:36 +00:00
Daniel Sanders
bb47fd04c9 [mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194471 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 10:45:18 +00:00
Bradley Smith
2ca352d027 [ARM] Add support for FP_HP_extension build attribute
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194470 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 10:38:05 +00:00
Daniel Sanders
aee7825762 [mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194469 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 10:31:49 +00:00
Daniel Sanders
d656c91aad [mips][msa] Change constant used in ori tests to avoid conflict with bseti (also xori to avoid bnegi)
Upcoming commit(s) are going to add support for bseti and bnegi. This would
cause some existing tests to (correctly) change behaviour and emit a different
instruction. This patch prevents this by changing the constant used in ori and
xori tests so that they will not be matchable by the bseti and bnegi patterns
when these instructions are matchable from normal IR.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194467 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 10:14:18 +00:00
Robert Lytton
47a4349eb6 XCore target: fix bug in aligning 'byval i8*' on the stack
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194466 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 10:11:35 +00:00
Robert Lytton
092815ce4b XCore target test for hidden declaration
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194465 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 10:11:30 +00:00
Robert Lytton
32e8528c33 Add XCore support for ATOMIC_FENCE.
ATOMIC_FENCE is lowered to a compiler barrier which is codegen only. There
is no need to emit an instructions since the XCore provides sequential
consistency.

Original patch by Richard Osborne

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194464 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 10:11:26 +00:00
Robert Lytton
c17ea93ed5 XCore target: return error for unsupported alignment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194463 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 10:11:05 +00:00
Yuchen Wu
0cbecb56fb Revert "Added basic unit test for llvm-cov."
This reverts commit r194451.

Not sure why the tests are failing on the buildbot. They run fine on my
local machine. Could it possibly be because of the endianness of the
architectures? The GCNO and GCDA files are little-endian encoded, and
llvm-cov expects it to remain that way. Is this a safe assumption?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194454 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 05:57:06 +00:00
Yuchen Wu
f42264e7e4 llvm-cov: Added call to update run/program counts.
Also updated test files that were generated from this change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194453 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 04:59:08 +00:00
Yuchen Wu
d99e04db6a Added basic unit test for llvm-cov.
This test compares the output of llvm-cov against a coverage file
generated by gcov. Since the source file must be in the current
directory when reading GCNO files, the test will first cd into the
Inputs directory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194451 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 04:52:53 +00:00
Matt Arsenault
86245071b5 R600/SI: Change formatting of printed registers.
Print the range of registers used with a single letter prefix.
This better matches what the shader compiler produces and
is overall less obnoxious than concatenating all of the
subregister names together.

Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1,
it will print s[0:1] and so on.

There doesn't appear to be a straightforward way
to get the actual register info in the InstPrinter,
so this parses the generated name to print with the
new syntax.

The required test changes are pretty nasty, and register
matching regexes are now worse. Since there isn't a way to
add to a variable in FileCheck, some of the tests now don't
check the exact number of registers used, but I don't think that
will be a real problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194443 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 02:35:51 +00:00
Reed Kotler
c6d4d667a8 Change the default branch instruction to be the 16 bit variety for mips16.
This has no material effect at this time since we don't have a direct
object emitter for mips16 and the assembler can't tell them apart. I
place a comment "16 bit inst" for those so that I can tell them apart in the
output. The constant island pass has only been minimally changed to allow
this. More complete branch work is forthcoming but this is the first
step.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194442 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 02:27:12 +00:00
Matt Arsenault
e57a8a3d10 R600/SI: Add test that fails due to requiring i64 mul for pointers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194433 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 23:31:02 +00:00
Andrew Trick
01846af6ed Fix the recently added anyregcc convention to handle spilled operands.
Fixes <rdar://15432754> [JS] Assertion: "Folded a def to a non-store!"

The primary purpose of anyregcc is to prevent a patchpoint's call
arguments and return value from being spilled. They must be available
in a register, although the calling convention does not pin the
register. It's up to the front end to avoid using this convention for
calls with more arguments than allocatable registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194428 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 22:40:25 +00:00
Vincent Lejeune
70a7d5ddb4 R600: Use function inputs to represent data stored in gpr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194425 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 22:10:24 +00:00
Shuxin Yang
6c7a7c6474 Fix PR17952.
The symptom is that an assertion is triggered. The assertion was added by
me to detect the situation when value is propagated from dead blocks.
(We can certainly get rid of assertion; it is safe to do so, because propagating
 value from dead block to alive join node is certainly ok.)

  The root cause of this bug is : edge-splitting is conducted on the fly,
the edge being split could be a dead edge, therefore the block that 
split the critial edge needs to be flagged "dead" as well.

  There are 3 ways to fix this bug:
  1) Get rid of the assertion as I mentioned eariler 
  2) When an dead edge is split, flag the inserted block "dead".
  3) proactively split the critical edges connecting dead and live blocks when
     new dead blocks are revealed.

  This fix go for 3) with additional 2 LOC.

  Testing case was added by Rafael the other day.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194424 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 22:00:23 +00:00
Akira Hatanaka
5635de519a [mips] Partially revert r193641. Stack alignment should not be determined by
the floating point register mode.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194423 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 21:49:03 +00:00
Simon Atanasyan
fe9ce427d0 Add support for DT_VERxxx and DT_MIPS_xxx .dynamic section entries to the
llvm-readobj.

The patch reviewed by Michael Spencer.
http://llvm-reviews.chandlerc.com/D2113

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194421 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 20:51:48 +00:00
Artyom Skrobov
ef572e31e2 [ARM] Add support for MVFR2 which is new in ARMv8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194416 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 19:56:13 +00:00
Justin Holewinski
07a5d3dc3d [NVPTX] Properly handle bitcast ConstantExpr when checking for the alignment of function parameters
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194410 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 19:28:19 +00:00
Justin Holewinski
0df3ce333b [NVPTX] Fix logic error in loading vector parameters of more than 4 components
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194409 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 19:28:16 +00:00
Chad Rosier
4c433cf673 [AArch64] The shift right/left and insert immediate builtins expect 3
source operands, a vector, an element to insert, and a shift amount.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194406 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 19:11:11 +00:00
Chad Rosier
30b2a19f3b [AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194394 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 18:04:07 +00:00
Daniel Sanders
028e4d27b1 Vector forms of SHL, SRA, and SRL can be constant folded using SimplifyVBinOp too
Reviewers: dsanders

Reviewed By: dsanders

CC: llvm-commits, nadav

Differential Revision: http://llvm-reviews.chandlerc.com/D1958

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194393 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 17:23:41 +00:00
Matheus Almeida
12f06e1e09 [mips][msa] CHECK-DAG-ize MSA 3r-a.ll test.
No functional changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194391 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 16:46:20 +00:00
Matheus Almeida
e7a21331b5 [mips][msa] CHECK-DAG-ize MSA 2rf_int_float.ll test.
No functional changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194390 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 16:38:55 +00:00
Matheus Almeida
9d48b69e37 [mips][msa] CHECK-DAG-ize MSA 2rf_float_int.ll test.
No functional changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194389 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 16:31:46 +00:00
Matheus Almeida
1b2034d969 [mips][msa] CHECK-DAG-ize MSA 2rf.ll test.
No functional changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194387 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 16:24:53 +00:00
Matheus Almeida
416a158893 [mips][msa] CHECK-DAG-ize MSA 2r.ll test.
No functional changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194386 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 16:16:53 +00:00
Rafael Espindola
a2b3882c10 Add a testcase for pr17852.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194385 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 15:37:52 +00:00
Hal Finkel
f14beced2b Add PPC option for full register names in asm
On non-Darwin PPC systems, we currently strip off the register name prefix
prior to instruction printing. So instead of something like this:

  mr r3, r4

we print this:

  mr 3, 4

The first form is the default on Darwin, and is understood by binutils, but not
yet understood by our integrated assembler. Once our integrated-as understands
full register names as well, this temporary option will be replaced by tying
this functionality to the verbose-asm option. The numeric-only form is
compatible with legacy assemblers and tools, and is also gcc's default on most
PPC systems. On the other hand, it is harder to read, and there are some
analysis tools that expect full register names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194384 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 14:58:40 +00:00
Peter Zotov
fa6ab4393e [OCaml] Add missing Llvm_target functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194382 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 14:47:28 +00:00
Peter Zotov
786a43e2d8 [OCaml] Accept context explicitly in Llvm_target functions
Llvm_target.intptr_type used to implicitly use global context. As
none of other functions in OCaml bindings do, it is changed to
accept context explicitly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194381 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 14:47:20 +00:00
Peter Zotov
26f3bd8966 [OCaml] Make Llvm_target.DataLayout.t automatically managed
This breaks the API by removing Llvm_target.DataLayout.dispose.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194380 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 14:47:11 +00:00
Evgeniy Stepanov
4590b8c090 [msan] Propagate origin for insertvalue, extractvalue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194374 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 13:37:10 +00:00
NAKAMURA Takumi
a22657f457 Mark 36 tests as XFAIL:vg_leak in llvm/test/TableGen.
In historical reason, tblgen is not strictly required to be free from memory leaks.
For now, I mark them as XFAIL, they could be fixed, though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194353 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-10 14:26:08 +00:00
NAKAMURA Takumi
c48f086d7c Remove 6 of XFAIL(s) in llvm/test/TableGen, since r193736. They have been XPASSing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194352 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-10 14:25:44 +00:00
Bill Wendling
855c29d82c Revert "Resurrect r191017 " GVN proceeds in the presence of dead code" plus a fix to PR17307 & 17308."
This causes PR17852.

This reverts commit d93e8a06b2.

Conflicts:
	test/Transforms/GVN/cond_br2.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194348 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-10 07:34:34 +00:00
Nadav Rotem
30150a128c SimplifyCFG has a heuristics for out-of-order processors that decides when it is worthwhile to merge branches. It tries to estimate if the operands of the instruction that we want to hoist are ready. This commit marks function arguments as 'ready' because they require no calculation. This boosts libquantum and a few other workloads from the testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194346 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-10 04:13:31 +00:00
Matt Arsenault
9c410777d1 Resolve TODO in test now that filecheck has multiple check prefixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194344 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-10 02:16:47 +00:00
Matt Arsenault
ee4f5eae1c Allow multiple check prefixes in FileCheck.
This is useful if you want to run multiple variations
of a single test, and the majority of check lines
should be the same.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194343 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-10 02:04:09 +00:00
Matt Arsenault
432bdf6571 Teach MergeFunctions about address spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194342 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-10 01:44:37 +00:00
Matt Arsenault
328c61d60c Use variable for register name in test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194338 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-10 00:57:17 +00:00
Reed Kotler
50d3b27f43 Mostly finish up constant islands port for Mips for load constants.
Still need to finish the branch part. Still lots more review of the code,
clean up and testing. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194337 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-10 00:09:26 +00:00
Akira Hatanaka
95830221bd [mips] Make sure there is a chain edge dependency between loads that read
formal arguments on the stack and stores created afterwards. We need this to
ensure tail call optimized function calls do not write over the argument area
of the stack before it is read out.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194309 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-09 02:38:51 +00:00
Juergen Ributzka
d4f5a61567 [Stackmap] Materialize the jump address within the patchpoint noop slide.
This patch moves the jump address materialization inside the noop slide. This
enables patching of the materialization itself or its complete removal. This
patch also adds the ability to define scratch registers that can be used safely
by the code called from the patchpoint intrinsic. At least one scratch register
is required, because that one is used for the materialization of the jump
address. This patch depends on D2009.

Differential Revision: http://llvm-reviews.chandlerc.com/D2074

Reviewed by Andy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194306 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-09 01:51:33 +00:00
Juergen Ributzka
623d2e618f [Stackmap] Add AnyReg calling convention support for patchpoint intrinsic.
The idea of the AnyReg Calling Convention is to provide the call arguments in
registers, but not to force them to be placed in a paticular order into a
specified set of registers. Instead it is up tp the register allocator to assign
any register as it sees fit. The same applies to the return value (if
applicable).

Differential Revision: http://llvm-reviews.chandlerc.com/D2009

Reviewed by Andy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194293 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 23:28:16 +00:00
Jim Grosbach
dc7eb3e023 X86: Assembly files with .cfi_cfa_def shouldn't hit llvm_unreachable()
On darwin, when trying to create compact unwind info, a .cfi_cfa_def
directive would case an llvm_unreachable() to be hit. Back off when we
see this directive and generate the regular DWARF style eh_frame.

rdar://15406518

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194285 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 22:33:06 +00:00
Quentin Colombet
f0c6ab6f00 [VirtRegMap] Fix for PR17825. Do not ignore noreturn definitions when setting
isPhysRegUsed if the unwind information is required.
Indeed, the runtime may need a correct stack to be able to unwind the call.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194271 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 18:14:17 +00:00
Tim Northover
323ac85d6a ARM: fold prologue/epilogue sp updates into push/pop for code size
ARM prologues usually look like:
    push {r7, lr}
    sub sp, sp, #4

If code size is extremely important, this can be optimised to the single
instruction:
    push {r6, r7, lr}

where we don't actually care about the contents of r6, but pushing it subtracts
4 from sp as a side effect.

This should implement such a conversion, predicated on the "minsize" function
attribute (-Oz) since I've yet to find any code it actually makes faster.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194264 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 17:18:07 +00:00
Artyom Skrobov
2b01682aa7 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (Thumb encodings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194263 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 16:25:50 +00:00
Artyom Skrobov
c5c991bf31 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194262 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 16:17:14 +00:00
Artyom Skrobov
fa840ba402 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194261 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 16:16:30 +00:00
Zoran Jovanovic
c9af1add85 Test for microMIPS trap instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194258 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 14:55:31 +00:00
NAKAMURA Takumi
6af8781854 llvm-ar: Let opening a directory failed in llvm-ar.
Linux cannot open directories with open(2), although cygwin and *bsd can.

Motivation: The test, Object/directory.ll, had been failing with --target=cygwin on Linux. XFAIL was improper for host issues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194257 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 12:35:56 +00:00
Matheus Almeida
de712386cd [mips][msa] Update encoding of LDI instruction.
The encoding was updated in MSA r1.07.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194255 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 10:43:11 +00:00
Artyom Skrobov
1b91231347 [ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194253 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 09:16:31 +00:00
David Majnemer
0ab2058852 IR: Do not canonicalize constant GEPs into an out-of-bounds array access
Summary:
Consider a GEP of:
i8* getelementptr ({ [2 x i8], i32, i8, [3 x i8] }* @main.c, i32 0, i32 0, i64 0)

If we proceeded to GEP the aforementioned object by 8, would form a GEP of:
i8* getelementptr ({ [2 x i8], i32, i8, [3 x i8] }* @main.c, i32 0, i32 0, i64 8)

Note that we would go through the first array member, causing an
out-of-bounds accesses.  This is problematic because we might get fooled
if we are trying to evaluate loads using this GEP, for example, based
off of an object with a constant initializer where the array is zero.

This fixes PR17732.

Reviewers: nicholas, chandlerc, void

Reviewed By: void

CC: llvm-commits, echristo, void, aemerson

Differential Revision: http://llvm-reviews.chandlerc.com/D2093

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-07 22:15:53 +00:00
Zoran Jovanovic
9f471750fa Support for microMIPS trap instructions 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194205 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-07 14:35:24 +00:00
Vincent Lejeune
69239a98b6 R600: Fix LowerUDIVREM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194153 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 17:36:04 +00:00
Benjamin Kramer
02707cb98e Add test case for PR12377, it was fixed by r194116.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194147 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 11:55:41 +00:00
Vladimir Medic
2263a2ca72 Implement gpword directive for mips, test case added. Stype changes using clang-format are also included.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194145 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 11:27:05 +00:00
Peter Zotov
ec7270c966 [OCaml] Impement Llvm_irreader, bindings to LLVM assembly parser
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194138 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 09:21:25 +00:00
Peter Zotov
ba0c7cd012 [OCaml] Implement Llvm.string_of_llvalue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194136 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 09:21:08 +00:00
Jiangning Liu
8458f371b8 Implement AArch64 Neon instruction set Perm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 03:35:27 +00:00
Jiangning Liu
258115258f Implement AArch64 Neon instruction set Bitwise Extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194118 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 02:25:49 +00:00
Andrew Trick
10bb82e54f Rewrite SCEV's backedge taken count computation.
Patch by Michele Scandale!

Rewrite of the functions used to compute the backedge taken count of a
loop on LT and GT comparisons.

I decided to split the handling of LT and GT cases becasue the trick
"a > b == -a < -b" in some cases prevents the trip count computation
due to the multiplication by -1 on the two operands of the
comparison. This issue comes from the conservative computation of
value range of SCEVs: taking the negative SCEV of an expression that
have a small positive range (e.g. [0,31]), we would have a SCEV with a
fullset as value range.

Indeed, in the new rewritten function I tried to better handle the
maximum backedge taken count computation when MAX/MIN expression are
used to handle the cases where no entry guard is found.

Some test have been modified in order to check the new value correctly
(I manually check them and reasoning on possible overflow the new
values seem correct).

I finally added a new test case related to the multiplication by -1
issue on GT comparisons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194116 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 02:08:26 +00:00
Andrew Trick
dc8224def3 Slightly change the way stackmap and patchpoint intrinsics are lowered.
MorphNodeTo is not safe to call during DAG building. It eagerly
deletes dependent DAG nodes which invalidates the NodeMap. We could
expose a safe interface for morphing nodes, but I don't think it's
worth it. Just create a new MachineNode and replaceAllUsesWith.

My understaning of the SD design has been that we want to support
early target opcode selection. That isn't very well supported, but
generally works. It seems reasonable to rely on this feature even if
it isn't widely used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194102 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 22:44:04 +00:00
Tim Northover
f635ab8eab ARM: permit bare dmb/dsb/isb aliases on Cortex-M0
Cortex-M0 supports these 32-bit instructions despite being Thumb1 only
(mostly). We knew about that but not that the aliases without the default "sy"
operand were also permitted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194094 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 21:36:02 +00:00
Jiangning Liu
3ff3a8aa75 Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194085 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 17:42:05 +00:00
Michael Gottesman
f23af8bfd8 [objc-arc] Convert the one directional retain/release relation assert to a conditional check + fail.
Due to the previously added overflow checks, we can have a retain/release
relation that is one directional. This occurs specifically when we run into an
additive overflow causing us to drop state in only one direction. If that
occurs, we should bail and not optimize that retain/release instead of
asserting.

Apologies for the size of the testcase. It is necessary to cause the additive
cfg overflow to trigger.

rdar://15377890

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 16:02:40 +00:00
Alp Toker
04ae34b0aa Provide a test input for opt
This was only working previously due to a quirk in the way lit
concatenates script commands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194078 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 13:57:34 +00:00
Peter Zotov
c8ac229cc8 [OCaml] (PR16318) Add missing argument to Llvm.const_intcast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194065 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 11:56:20 +00:00
Peter Zotov
150c95eab5 [OCaml] (PR11717) Make declare_qualified_global respect address argument
Original patch by Jonathan Ragan-Kelley

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194064 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 11:56:13 +00:00
Reed Kotler
c0e9800d45 Fix r194019 as requested by Eric Christopher.
Submit the basic port of the rest of ARM constant islands code to Mips. 
Two test cases are added which reflect the next level of functionality:
constants getting moved to water areas that are out of range from the
initial placement at the end of the function and basic blocks being split to
create water when none exists that can be used. There is a bunch of this
code that is not complete and has been marked with IN_PROGRESS. I will
finish cleaning this all up during the next week or two and submit the
rest of the test cases. I have elminated some code for dealing with
inline assembly because to me it unecessarily complicates things and
some of the newer features of llvm like function attributies and builtin
assembler give me better tools to solve the alignment issues created
there. Also, for Mips16 I even have the option of not doing constant
islands in the present of inline assembler if I chose. When everything
has been completed I will summarize the port and notify people that
are knowledgable regarding the ARM Constant Islands code so they can
review it in it's entirety if they wish.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194053 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 08:14:14 +00:00
Hao Liu
591c2f738a Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post).
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194043 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 03:39:32 +00:00
Kevin Qin
8263dcdf23 Implemented aarch64 neon intrinsic vcopy_lane with float type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194041 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 02:03:59 +00:00
Yuchen Wu
e6bfdf92d3 Revert "Added basic unit test for llvm-cov."
This reverts commit 9cacd131c22b888303cb88e9a3235b2d7b2f19a1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194039 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 01:56:26 +00:00
Yuchen Wu
07a59fbd3b Added basic unit test for llvm-cov.
This test compares the output of llvm-cov against a coverage file
generated by gcov.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194038 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 01:56:23 +00:00
NAKAMURA Takumi
225f35a87c Revert r194019 to r194021, "Submit the basic port of the rest of ARM constant islands code to Mips."
It broke -Asserts build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194026 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 23:14:36 +00:00
Tim Northover
627ef0cf5e AArch64: use default asm operand printing when modifier inapplicable
If an inline assembly operand has multiple constraints (e.g. "Ir" for immediate
or register) and an operand modifier (E.g. "w" for "print register as wN") then
we need to decide behaviour when the modifier doesn't apply to the constraint.

Previousely produced some combination of an assertion failure and a fatal
error. GCC's behaviour appears to be to ignore the modifier and print the
operand in the default way. This patch should implement that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194024 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 23:04:07 +00:00
Reed Kotler
9157a7eecb Add the test case that goes with the previous submission for constant
islands. I forgot to add it to svn on that patch. Ooops.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194020 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 22:13:41 +00:00
Eric Christopher
3faf43fc66 Check for both styles of clobbers, those produced by dragonegg and
those produced by clang for the inline asm bswap conversion.

Modified from a patch by Chris Smowton.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194016 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 21:41:21 +00:00
Matt Arsenault
896a885f21 Fix another constant folding address space place I missed.
This fixes an assertion failure with a different sized address space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194014 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 20:46:52 +00:00
Matt Arsenault
eba6d38448 Scalarize select vector arguments when extracted.
When the elements are extracted from a select on vectors
or a vector select, do the select on the extracted scalars
from the input if there is only one use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194013 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 20:36:06 +00:00
Cameron McInally
2e58f1d4cf Add support for AVX512 masked vector blend intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194006 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 19:14:56 +00:00
Manman Ren
827ffff4b1 Rename testing case to use - instead of _.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194001 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 18:52:06 +00:00
Rafael Espindola
e076b5338a Change BitcodeReader to use error_code instead of bool + string.
In order to create an ObjectFile implementation that uses bitcode files, we
need to propagate the bitcode errors to the ObjectFile interface, so we need
to convert it to use the same error handling as ObjectFile: error_code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193996 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 16:16:24 +00:00
Zoran Jovanovic
5c042162be Support for microMIPS branch instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193992 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 14:53:22 +00:00
Peter Zotov
4ebe64ae7e [OCaml] implement Llvm_passmgr_builder, bindings for PassManagerBuilder
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193968 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 01:39:42 +00:00
Peter Zotov
8a3bdd6a3f [OCaml] Implement missing LLVMCore APIs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193966 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 01:39:26 +00:00
Elena Demikhovsky
633f98bdfa AVX-512: added VPCONFLICT instruction and intrinsics,
added EVEX_KZ to tablegen


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193959 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-03 13:46:31 +00:00
Venkatraman Govindaraju
fcd5e86396 [SparcV9] Handle i64 <-> float conversions in sparcv9 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193957 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-03 12:28:40 +00:00
David Majnemer
16d1098718 Revert "Inliner: Handle readonly attribute per argument when adding memcpy"
This reverts commit r193356, it caused PR17781.

A reduced test case covering this regression has been added to the test suite.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193955 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-03 12:22:13 +00:00
Peter Zotov
f00a9e0f79 [OCaml] Implement Llvm.MemoryBuffer.{of_string,as_string}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193953 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-03 08:27:45 +00:00
Peter Zotov
9d33bf70c2 [OCaml] Implement Llvm_linker, bindings for the IR linker
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193951 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-03 08:27:32 +00:00
Peter Zotov
1185582dfd [OCaml] Implement Llvm_vectorize bindings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193950 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-03 08:27:22 +00:00
Peter Zotov
6ca1789ac6 [OCaml] Refactor Llvm_target tests
Llvm_target tests did not check for return values. This actually
caused them to miss a bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193949 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-03 08:27:13 +00:00
Venkatraman Govindaraju
5e45051e0e [Sparc] Expand FP_TO_UINT, UINT_TO_FP for fp128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193947 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-03 08:00:19 +00:00
Peter Zotov
30288ac402 [OCaml] Llvm_scalar_opts: add missing transforms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193946 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-03 07:54:17 +00:00
Peter Zotov
630109d30c [OCaml] Llvm_ipo: add missing transforms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193945 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-03 07:54:08 +00:00
Bob Wilson
208130f113 Convert calls to __sinpi and __cospi into __sincospi_stret
This adds an SimplifyLibCalls case which converts the special __sinpi and
__cospi (float & double variants) into a __sincospi_stret where appropriate to
remove duplicated work.

Patch by Tim Northover

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193943 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-03 06:48:38 +00:00
Bob Wilson
cb01efb798 Enable optimization of sin / cos pair into call to __sincos_stret for iOS7+.
rdar://12856873
Patch by Evan Cheng, with a fix for rdar://13209539 by Tilmann Scheller

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193942 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-03 06:14:38 +00:00
Venkatraman Govindaraju
11cecbe1a0 [SparcV9] Add ctpop instruction for i64. Also, expand ctlz, cttz and bswap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193941 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-03 05:59:07 +00:00
Rafael Espindola
bd2affeab4 A better fix that also works on ppc: add a target tripple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193915 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-02 06:00:09 +00:00
Rafael Espindola
e62e056766 Fix this test to pass on darwin now that llvm-nm is working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193914 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-02 05:29:22 +00:00
Rafael Espindola
6152f7d596 Fix llvm-nm to mach OS X's nm on some tests.
There is still a long way to go for llvm-nm, but at least we now match
nm's letter output in the cases we test for.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193912 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-02 05:03:24 +00:00
Michael Liao
9d293f1f68 Fix PR17764
- When selecting BLEND from vselect, the operands need swapping as due to the
  difference between vselect and SSE/AVX's BLEND insn



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193900 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-02 00:10:02 +00:00
David Blaikie
96bf70c13b DebugInfo: regenerate test case from Clang to adjust for fixes/improvements
I hit some problems with future work due to the member subprogram of
'a_b's type having a subprogram (an implicit default ctor, !52 in the
pre-commit source) with no name. Clang now generates a name for such a
function but in this case doesn't even emit debug info for it as it is
unused (Clang never emits the body of the ctor, instead just emitting
memset if needed).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193892 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 22:29:28 +00:00
Arnold Schwaighofer
f4775827d0 LoopVectorizer: Perform redundancy elimination on induction variables
When the loop vectorizer was part of the SCC inliner pass manager gvn would
run after the loop vectorizer followed by instcombine. This way redundancy
(multiple uses) were removed and instcombine could perform scalarization on the
induction variables. Having moved the loop vectorizer to later we no longer run
any form of redundancy elimination before we perform instcombine. This caused
vectorized induction variables to survive that did not before.

On a recent iMac this helps linpack back from 6000Mflops to 7000Mflops.

This should also help lpbench and paq8p.

I ran a Release (without Asserts) build over the test-suite and did not see any
negative impact on compile time.

radar://15339680

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193891 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 22:18:19 +00:00
David Blaikie
4b1d68bca9 DebugInfo: Improve readability of test case added in r193878
The point is to ensure that the attribute in question
(DW_AT_data_member_location) is associated with the prior tag, so ensure
that we don't see another tag starting between the intended tag and the
desired attribute.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193884 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 20:59:53 +00:00
David Blaikie
84b418a997 DebugInfo: add a test case for data member locations (coverage for r193835)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193878 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 18:25:55 +00:00
David Blaikie
81d0b3c513 Fix a test case broken by r193872
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193876 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 18:18:16 +00:00
Manman Ren
cc14cb31d4 Add comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193874 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 18:06:25 +00:00
David Blaikie
2e110c3fa6 DebugInfo: Make pubnames header printing similar to unit header printing
In a failed attempt to allow the gnu-public-names.ll test case to not
hardcode the size of the unit that the pubnames section referred to I've
at least managed to have unit headers and pubnames headers print out in
a similar style.

This failed to achieve the desired goal because the header in a unit
specifies the length of the unit without the length element of the
header whereas the length in the pubnames includes this element, so the
numbers are off by 4 bytes. I don't know of any arithmetic powers in
FileCheck so the test case can't simply say "CU_LENGTH + 4".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193872 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 17:53:30 +00:00
Benjamin Kramer
7208b0763c LoopVectorize: Look for consecutive acces in GEPs with trailing zero indices
If we have a pointer to a single-element struct we can still build wide loads
and stores to it (if there is no padding).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193860 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 14:09:50 +00:00
Bradley Smith
6186de5c54 [ARM] Add Virtualization subtarget feature and more build attributes in this area
Add a Virtualization ARM subtarget feature along with adding proper build
attribute emission for Tag_Virtualization_use (encodes Virtualization and
TrustZone) and Tag_MPextension_use.

Also rework test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll testcase to
something that is more maintainable. This changes the focus of this
testcase away from testing CPU defaults (which is tested elsewhere), onto
specifically testing that attributes are encoded correctly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193859 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 13:27:35 +00:00
Bradley Smith
479a2de32a [ARM] Fix Tag_ABI_HardFP_use build attribute
Fix Tag_ABI_HardFP_use build attribute to handle single precision FP,
replace deprecated Tag_ABI_HardFP_use value of 3 with 0 and also add
some tests for Tag_ABI_VFP_args.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193856 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 11:21:16 +00:00
Hal Finkel
e14fb07357 Consider (x == -1) unlikely in BranchProbabilityInfo
This adds another heuristic to BPI, similar to the existing heuristic that
considers (x == 0) unlikely to be true. As suggested in the PACT'98 paper by
Deitrich, Cheng, and Hwu, -1 is often used to indicate an invalid index, and
equality comparisons with -1 are also unlikely to succeed. Local
experimentation supports this hypothesis: This yields a 1-2% speedup in the
test-suite sqlite benchmark on the PPC A2 core, with no significant
regressions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193855 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 10:58:22 +00:00
Arnold Schwaighofer
0097e15502 LoopVectorizer: If dependency checks fail try runtime checks
When a dependence check fails we can still try to vectorize loops with runtime
array bounds checks.

This helps linpack to vectorize a loop in dgefa. And we are back to 2x of the
scalar performance on a corei7-avx.

radar://15339680

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193853 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 03:05:07 +00:00
Rafael Espindola
56ca8b3059 Use \01 to disable the mangler. Should fix the 32 bit windows bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193846 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 01:14:20 +00:00
David Blaikie
9b93392185 DebugInfo: Emit member variable locations as data instead of expressions in blocks
Drive by space optimization. Also makes the DIEs more regular which
might speed up DWARF parsing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193835 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-01 00:25:45 +00:00
Andrew Trick
6c4594f5b8 These test cases for experimental features are a bit too darwin-specific still. Use a triple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193820 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 22:46:51 +00:00
Chad Rosier
1a035dd6df [AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193816 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 22:36:59 +00:00
Andrew Trick
2ddc56dec8 Add new calling convention for WebKit Java Script.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193812 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 22:12:01 +00:00
Andrew Trick
3d74dea4bd Add support for stack map generation in the X86 backend.
Originally implemented by Lang Hames.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193811 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 22:11:56 +00:00
Rafael Espindola
53446e50a0 Relax check line to match what llvm-nm prints for COFF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193810 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 22:07:46 +00:00
Manman Ren
ef34496b3f Do not convert "call asm" to "invoke asm" in Inliner.
Given that backend does not handle "invoke asm" correctly ("invoke asm" will be
handled by SelectionDAGBuilder::visitInlineAsm, which does not have the right
setup for LPadToCallSiteMap) and we already made the assumption that inline asm
does not throw in InstCombiner::visitCallSite, we are going to make the same
assumption in Inliner to make sure we don't convert "call asm" to "invoke asm".

If it becomes necessary to add support for "invoke asm" later on, we will need
to modify the backend as well as remove the assumptions that inline asm does
not throw.

Fix rdar://15317907


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193808 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 21:56:03 +00:00
Rafael Espindola
fe0ae1db3a XFAIL on ppc64 too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193804 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 21:27:02 +00:00
Rafael Espindola
6af049837a XFAIL this for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193802 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 21:22:43 +00:00
Rafael Espindola
7e667c56cf Use LTO_SYMBOL_SCOPE_DEFAULT_CAN_BE_HIDDEN instead of the "dso list".
There are two ways one could implement hiding of linkonce_odr symbols in LTO:
* LLVM tells the linker which symbols can be hidden if not used from native
  files.
* The linker tells LLVM which symbols are not used from other object files,
  but will be put in the dso symbol table if present.

GOLD's API is the second option. It was implemented almost 1:1 in llvm by
passing the list down to internalize.

LLVM already had partial support for the first option. It is also very similar
to how ld64 handles hiding these symbols when *not* doing LTO.

This patch then
* removes the APIs for the DSO list.
* marks LTO_SYMBOL_SCOPE_DEFAULT_CAN_BE_HIDDEN all linkonce_odr unnamed_addr
  global values and other linkonce_odr whose address is not used.
* makes the gold plugin responsible for handling the API mismatch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193800 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 20:51:58 +00:00
Chad Rosier
f7ba489730 [AArch64] Add diagnostic tests for NEON scalar shift immediate instructions (see: r193790).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193798 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 20:11:32 +00:00
Chad Rosier
1d28917dc3 [AArch64] Add support for NEON scalar shift immediate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193790 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 19:28:44 +00:00
Roman Divacky
1d6d49fbb1 SparcV9 doesnt have rem instruction either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193789 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 19:22:33 +00:00
Reid Kleckner
844e7d35d4 Use a larger invalid attribute bitcode number
That way the test won't start faililng when someone adds a new attribute
and wants to use the next logical enum (38) for bitcode.  The new
bitcode file tries to use the number 48 as an attribute instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193787 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 19:12:36 +00:00
Matt Arsenault
67b52144d2 Add FileCheck tests for @LINE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193782 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 18:18:09 +00:00
Petar Jovanovic
4999ae9cfa [mips] XFAIL several MCJIT remote tests
Two of the tests are new test cases (cross-module-a.ll, multi-module-a.ll)
not yet supported on MIPS, while XFAIL for the other two tests was
accidentally removed in r193570 and this change reverts those lines.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193781 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 18:10:25 +00:00
Manman Ren
b8b70e10a2 Debug Info: remove duplication of DIEs when a DIE can be shared across CUs.
We add a map in DwarfDebug to map MDNodes that are shareable across CUs to the
corresponding DIEs: MDTypeNodeToDieMap. These DIEs can be shared across CUs,
that is why we keep the maps in DwarfDebug instead of CompileUnit.

We make the assumption that if a DIE is not added to an owner yet, we assume
it belongs to the current CU. Since DIEs for the type system are added to
their owners immediately after creation, and other DIEs belong to the current
CU, the assumption should be true.

A testing case is added to show that we only create a single DIE for a type
MDNode and we use ref_addr to refer to the type DIE.

We also add a testing case to show ref_addr relocations for non-darwin
platforms.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193779 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 17:54:35 +00:00
Roman Divacky
6d6e66a3ee Merge and filecheckize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193778 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 17:50:45 +00:00
Andrew Trick
233012c25b Add Verifier test case for variable argument intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193768 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 17:18:17 +00:00
Andrew Trick
2e50b8a08d Enable variable arguments support for intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193766 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 17:18:11 +00:00
Cameron McInally
424f19732e Add AVX512 unmasked integer broadcast intrinsics and support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193748 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 13:56:31 +00:00
Elena Demikhovsky
f3280b5860 AVX-512: Implemented CMOV for 512-bit vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193747 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 13:15:32 +00:00
Richard Sandiford
793ce99ea7 [SystemZ] Automatically detect zEC12 and z196 hosts
As on other hosts, the CPU identification instruction is priveleged,
so we need to look through /proc/cpuinfo.  I copied the PowerPC way of
handling "generic".

Several tests were implicitly assuming z10 and so failed on z196.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193742 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 12:14:17 +00:00
Amara Emerson
c2884320fe [AArch64] Make the use of FP instructions optional, but enabled by default.
This adds a new subtarget feature called FPARMv8 (implied by NEON), and
predicates the support of the FP instructions and registers on this feature.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193739 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 09:32:11 +00:00
NAKAMURA Takumi
0f5e68e3dc llvm/test/Bitcode/invalid.ll: Tweak expresion to mach "llvm-dis.EXE:"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193738 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 06:21:00 +00:00
Rafael Espindola
cc8c673e61 Fix a use after free on invalid input.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193737 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 04:20:23 +00:00
Jim Grosbach
0e536ee4ca Legalize: Improve legalization of long vector extends.
When an extend more than doubles the size of the elements (e.g., a zext
from v16i8 to v16i32), the normal legalization method of splitting the
vectors will run into problems as by the time the destination vector is
legal, the source vector is illegal. The end result is the operation
often becoming scalarized, with the typical horrible performance. For
example, on x86_64, the simple input of:
define void @bar(<16 x i8> %a, <16 x i32>* %p) nounwind {
  %tmp = zext <16 x i8> %a to <16 x i32>
  store <16 x i32> %tmp, <16 x i32>*%p
  ret void
}

Generates:
  .section  __TEXT,__text,regular,pure_instructions
  .section  __TEXT,__const
  .align  5
LCPI0_0:
  .long 255                     ## 0xff
  .long 255                     ## 0xff
  .long 255                     ## 0xff
  .long 255                     ## 0xff
  .long 255                     ## 0xff
  .long 255                     ## 0xff
  .long 255                     ## 0xff
  .long 255                     ## 0xff
  .section  __TEXT,__text,regular,pure_instructions
  .globl  _bar
  .align  4, 0x90
_bar:
  vpunpckhbw  %xmm0, %xmm0, %xmm1
  vpunpckhwd  %xmm0, %xmm1, %xmm2
  vpmovzxwd %xmm1, %xmm1
  vinsertf128 $1, %xmm2, %ymm1, %ymm1
  vmovaps LCPI0_0(%rip), %ymm2
  vandps  %ymm2, %ymm1, %ymm1
  vpmovzxbw %xmm0, %xmm3
  vpunpckhwd  %xmm0, %xmm3, %xmm3
  vpmovzxbd %xmm0, %xmm0
  vinsertf128 $1, %xmm3, %ymm0, %ymm0
  vandps  %ymm2, %ymm0, %ymm0
  vmovaps %ymm0, (%rdi)
  vmovaps %ymm1, 32(%rdi)
  vzeroupper
  ret

So instead we can check if there are legal types that enable us to split
more cleverly when the input vector is already legal such that we don't
turn it into an illegal type. If the extend is such that it's more than
doubling the size of the input we check if
  - the number of vector elements is even,
  - the source type is legal,
  - the type of a split source is illegal,
  - the type of an extended (by doubling element size) source is legal, and
  - the type of that extended source when split is legal.
If the conditions are met, instead of just splitting both the
destination and the source types, we create an extend that only goes up
one "step" (doubling the element width), and the continue legalizing the
rest of the operation normally. The result is that this operates as a
new, more effecient, termination condition for the loop of "split the
operation until the destination type is legal."

With this change, the above example now compiles to:
_bar:
  vpxor %xmm1, %xmm1, %xmm1
  vpunpcklbw  %xmm1, %xmm0, %xmm2
  vpunpckhwd  %xmm1, %xmm2, %xmm3
  vpunpcklwd  %xmm1, %xmm2, %xmm2
  vinsertf128 $1, %xmm3, %ymm2, %ymm2
  vpunpckhbw  %xmm1, %xmm0, %xmm0
  vpunpckhwd  %xmm1, %xmm0, %xmm3
  vpunpcklwd  %xmm1, %xmm0, %xmm0
  vinsertf128 $1, %xmm3, %ymm0, %ymm0
  vmovaps %ymm0, 32(%rdi)
  vmovaps %ymm2, (%rdi)
  vzeroupper
  ret

This generalizes a custom lowering that was added a while back to the
ARM backend. That lowering is no longer necessary, and is removed. The
testcases for it, however, provide excellent ARM tests for this change
and so remain.

rdar://14735100

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193727 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 00:20:48 +00:00
Matt Arsenault
4f17f88071 Fix CodeGen for unaligned loads with address spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193721 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 23:30:05 +00:00
Matt Arsenault
9effcbb879 Teach scalarrepl about address spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193720 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 22:54:58 +00:00
Rafael Espindola
2cc546db18 Produce .weak_def_can_be_hidden for some linkonce_odr values
With this patch llvm produces a weak_def_can_be_hidden for linkonce_odr
if they are also unnamed_addr or don't have their address taken.

There is not a lot of documentation about .weak_def_can_be_hidden, but
from the old discussion about linkonce_odr_auto_hide and the name of
the directive this looks correct: these symbols can be hidden.

Testing this with the ld64 in Xcode 5 linking clang reduces the number of
exported symbols from 21053 to 19049.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193718 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 22:08:11 +00:00
Will Dietz
b7b1abef25 Add DebugInfo testcase for high_pc encoded as constant, fixed in r193555.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193711 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 20:27:17 +00:00
Matt Arsenault
b7ff48e374 Fix GVN creating bitcast between address spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193710 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 19:05:41 +00:00
Tom Roeder
4ca9a2a0ad This commit adds some (but not all) of the x86-64 relocations that are not
currently supported in the ELF object writer, along with a simple test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193709 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 18:47:25 +00:00
Artyom Skrobov
3f04b50686 [ARM] NEON instructions were erroneously decoded from certain invalid encodings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193705 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 18:10:09 +00:00
Tom Stellard
aa1d078e7f R600: Custom lower f32 = uint_to_fp i64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193701 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 17:22:05 +00:00
Daniel Sanders
02fbffd4e8 [mips][msa] Correct definition of bins[lr] and CHECK-DAG-ize related tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193695 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 15:45:42 +00:00
Daniel Sanders
c385709d83 [mips][msa] Added support for matching bmnz, bmnzi, bmz, and bmzi from normal IR (i.e. not intrinsics)
Also corrected the definition of the intrinsics for these instructions (the
result register is also the first operand), and added intrinsics for bsel and
bseli to clang (they already existed in the backend).

These four operations are mostly equivalent to bsel, and bseli (the difference
is which operand is tied to the result). As a result some of the tests changed
as described below.

bitwise.ll:
- bsel.v test adapted so that the mask is unknown at compile-time. This stops
  it emitting bmnzi.b instead of the intended bsel.v.
- The bseli.b test now tests the right thing. Namely the case when one of the
  values is an uimm8, rather than when the condition is a uimm8 (which is
  covered by bmnzi.b)

compare.ll:
- bsel.v tests now (correctly) emits bmnz.v instead of bsel.v because this
  is the same operation (see MSA.txt).

i8.ll
- CHECK-DAG-ized test.
- bmzi.b test now (correctly) emits equivalent bmnzi.b with swapped operands
  because this is the same operation (see MSA.txt).
- bseli.b still emits bseli.b though because the immediate makes it
  distinguishable from bmnzi.b.

vec.ll:
- CHECK-DAG-ized test.
- bmz.v tests now (correctly) emits bmnz.v with swapped operands (see
  MSA.txt).
- bsel.v tests now (correctly) emits bmnz.v with swapped operands (see
  MSA.txt).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193693 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 15:20:38 +00:00
Chad Rosier
f853a034a1 [AArch64] Add support for NEON scalar floating-point compare instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193691 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 15:19:37 +00:00
Daniel Sanders
6ff1ef9931 [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics)
This required correcting the definition of the bins[lr]i intrinsics because
the result is also the first operand.

It also required removing the (arbitrary) check for 32-bit immediates in
MipsSEDAGToDAGISel::selectVSplat().

Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d
because the constant is legalized into a ConstantPool. Similar things can
happen with binsri.d with more than 10 bits set in the mask. The resulting
code when this happens is correct but not optimal.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193687 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 14:45:14 +00:00
Daniel Sanders
a7c3cac871 [mips][msa] Combine binsri-like DAG of AND and OR into equivalent VSELECT
(or (and $a, $mask), (and $b, $inverse_mask)) => (vselect $mask, $a, $b).
where $mask is a constant splat. This allows bitwise operations to make use
of bsel.

It's also a stepping stone towards matching bins[lr], and bins[lr]i from
normal IR.

Two sets of similar tests have been added in this commit. The bsel_* functions
test the case where binsri cannot be used. The binsr_*_i functions will
start to use the binsri instruction in the next commit.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193682 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 13:51:01 +00:00
Daniel Sanders
57cd3bc406 [mips][msa] Added support for matching splat.[bhw] from normal IR (i.e. not intrinsics)
splat.d is implemented but this subtest is currently disabled. This is because
it is difficult to match the appropriate IR on MIPS32. There is a patch under
review that should help with this so I hope to enable the subtest soon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193680 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 13:07:44 +00:00
Juergen Ributzka
9a5df73e32 Revert "SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too."
Now Hexagon and SystemZ are not happy with it :-(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193677 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 06:36:19 +00:00
Juergen Ributzka
4eced19c50 SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too.
The Type Legalizer recognizes that VSELECT needs to be split, because the type
is to wide for the given target. The same does not always apply to SETCC,
because less space is required to encode the result of a comparison. As a result
VSELECT is split and SETCC is unrolled into scalar comparisons.

This commit fixes the issue by checking for VSELECT-SETCC patterns in the DAG
Combiner. If a matching pattern is found, then the result mask of SETCC is
promoted to the expected vector mask type for the given target. This mask has
usually the same size as the VSELECT return type (except for Intel KNL). Now the
type legalizer will split both VSELECT and SETCC.

This allows the following X86 DAG Combine code to sucessfully detect the MIN/MAX
pattern. This fixes PR16695, PR17002, and <rdar://problem/14594431>.

Reviewed by Nadav

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193676 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 05:48:18 +00:00
Manman Ren
d498e5e960 Debug Info: instead of calling addToContextOwner which constructs the context
after the DIE creation, we construct the context first.

Ensure that we create the context before we create a type so that we can add
the newly created type to the parent. Remove last use of addToContextOwner
now that it's not needed.

We use createAndAddDIE to wrap around "new DIE(". Now all shareable DIEs
should be added to their parents right after the creation.

Reviewed off-list by Eric, Thanks.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193657 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 22:49:29 +00:00
Akira Hatanaka
615a279f81 [mips] Align the stack to 16-bytes for mfp64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193641 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 19:29:03 +00:00
Manman Ren
faf4ed2da8 Debug Info: clean up testing case.
Add a tag before the name attribute for readability. Use CHECK-NEXT
instead of CHECK-NOT followed by a CHECK. Add new lines to separate checking
of different DIEs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193629 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 17:27:14 +00:00
Weiming Zhao
a72ec5517f add test cases for frameaddr and returnaddr for aarch64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193626 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 17:01:29 +00:00
Zoran Jovanovic
1aaf43c2a2 Support for microMIPS jump instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193623 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 16:38:59 +00:00
Tom Stellard
54328c772c R600/SI: Add compute support for CI v2
v2:
  - Fix LDS size calculation

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193621 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 16:37:28 +00:00
Tom Stellard
f54a8409f9 R600: Expand vector FSQRT ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193620 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 16:37:20 +00:00
Bernard Ogden
c777b2e58c Test cleanup for v8 instructions
Add some missing tests, factor out a test not specific to v8 into
its own file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193611 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 14:16:09 +00:00
Bernard Ogden
47c6d17b1c ARM: Add subtarget feature for CRC
Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend.

Differential Revision: http://llvm-reviews.chandlerc.com/D2036

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193599 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 09:47:35 +00:00
Tim Northover
fd4937fe2a AArch64: add 'a' inline asm operand modifier
This is used in the Linux kernel, and effectively just means "print an
address".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193593 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 08:22:33 +00:00
Manman Ren
6b713800ff Debug Info: instead of calling addToContextOwner which constructs the context
after the DIE creation, we construct the context first.

This touches creation of namespaces and global variables. The purpose is to
handle all DIE creations similarly: constructs the context first, then creates
the DIE and immediately adds the DIE to its parent.

We use createAndAddDIE to wrap around "new DIE(".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193589 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 05:49:41 +00:00
NAKAMURA Takumi
b4e591a4a6 Add llvm/test/Transforms/SLPVectorizer/ARM/lit.local.cfg. Tests there require ARM in targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193580 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 02:46:00 +00:00
Alp Toker
18a988e3a7 Fix "existant" typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193579 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 02:35:28 +00:00
Arnold Schwaighofer
c04d241d13 ARM cost model: Unaligned vectorized double stores are expensive
Updated a test case that assumed that <2 x double> would vectorize to use
<4 x float>.

radar://15338229

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193574 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 01:33:57 +00:00
Arnold Schwaighofer
7e8cebf22d ARM cost model: Account for zero cost scalar SROA instructions
By vectorizing a series of srl, or, ... instructions we have obfuscated the
intention so much that the backend does not know how to fold this code away.

radar://15336950

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193573 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 01:33:53 +00:00
Andrew Kaylor
47b7fd5448 Adding a workaround for __main linking with remote lli and Cygwin/MinGW
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193570 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 01:29:56 +00:00
Joerg Sonnenberger
72580780a9 Move the STT_FILE symbols out of the normal symbol table processing for
ELF. They can overlap with the other symbols, e.g. if a source file
"foo.c" contains a function "foo" with a static variable "c".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 01:06:17 +00:00
Manman Ren
bbdd02cc30 Debug Info: use createAndAddDIE for newly-created Subprogram DIEs.
More patches will be submitted to convert "new DIE(" to use createAddAndDIE in
DwarfCompileUnit.cpp. This will simplify implementation of addDIEEntry where
we have to decide between ref4 and ref_addr, because DIEs that can be shared
across CU will be added to a CU already.

Reviewed off-list by Eric.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193567 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 00:58:04 +00:00
Andrew Kaylor
61e22ea592 Renaming MCJIT .ir files to .ll and moving them to Inputs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193562 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 23:51:03 +00:00
Alp Toker
1765daa21c lit: add missing substitutions for recently added tools
llvm-mcmarkup, obj2yaml and yaml2obj were missing from the substitutions list,
causing the test suite to fail in a sandboxed environment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193559 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 23:37:49 +00:00
Alp Toker
e794e41c35 Quote potential shell expansions found in tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193558 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 23:37:45 +00:00