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Author SHA1 Message Date
Hal Finkel
40be73bed7 Disallow i64 div/rem in PPC32 counter loops 
On PPC32, [su]div,rem on i64 types are transformed into runtime library
function calls. As a result, they are not allowed in counter-based loops (the
counter-loops verification pass caught this error; this change fixes PR16169).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183581 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 22:16:19 +00:00
Quentin Colombet
95f24fbe4c Revert commits related to stack warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183579 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 22:14:50 +00:00
Quentin Colombet
2e10e8e378 Explicit triple in warn stack size test cases to not depend on OS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183574 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 21:09:42 +00:00
Bill Wendling
e488b4ecdc Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183572 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 21:04:35 +00:00
Bill Wendling
a5e5ba611f Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183571 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 21:00:34 +00:00
Bill Wendling
1ce4985e01 Remove unused c'tor. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183570 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:59:31 +00:00
Tom Stellard
df74b86e1e R600: Fix calculation of stack offset in AMDGPUFrameLowering 
We weren't computing structure size correctly and we were relying on
the original alloca instruction to compute the offset, which isn't
always reliable.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183568 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:52:05 +00:00
Bill Wendling
fc61b6f111 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183567 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:42:15 +00:00
Tom Stellard
3ff0abfaab R600: Rework subtarget info and remove AMDILDevice classes 
This should simplify the subtarget definitions and make it easier to
add new ones.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183566 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:37:48 +00:00
Bill Wendling
c1dcb8d654 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183565 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:35:25 +00:00
Rui Ueyama
8b0f77bb96 [docs] Add link to Microsoft PE/COFF Spec. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183562 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:30:27 +00:00
Bill Wendling
b5632b5b45 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183561 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:28:55 +00:00
Tom Stellard
ce961477be R600: Fix the fetch limits for R600 generation GPUs 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>

https://bugs.freedesktop.org/show_bug.cgi?id=64257

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183560 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:28:55 +00:00
Tom Stellard
630547ada4 R600: Move Subtarget feature definitions into AMDGPU.td 
This is the convention used by the other targets.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183559 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:28:49 +00:00
Tom Stellard
6f3b49323c R600: Remove unnecessary include 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183558 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:28:43 +00:00
Eli Bendersky
88fe6824ee Add more explicit link targets to headers in LangRef.rst 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183555 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:24:43 +00:00
Quentin Colombet
9a6b9bffa5 Add a backend option to warn on a given stack size limit. 
Option: -mllvm -warn-stack-size=<limit>
Output (if limit is exceeded):
warning: Stack size limit exceeded (<actual size>) in <functionName>.

The longer term plan is to hook that to a clang warning.
PR:4072
<rdar://problem/13987214>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183552 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:18:12 +00:00
JF Bastien
8fc760cbe8 ARM FastISel integer sext/zext improvements 
My recent ARM FastISel patch exposed this bug:
  http://llvm.org/bugs/show_bug.cgi?id=16178
The root cause is that it can't select integer sext/zext pre-ARMv6 and
asserts out.

The current integer sext/zext code doesn't handle other cases gracefully
either, so this patch makes it handle all sext and zext from i1/i8/i16
to i8/i16/i32, with and without ARMv6, both in Thumb and ARM mode. This
should fix the bug as well as make FastISel faster because it bails to
SelectionDAG less often. See fastisel-ext.patch for this.

fastisel-ext-tests.patch changes current tests to always use reg-imm AND
for 8-bit zext instead of UXTB. This simplifies code since it is
supported on ARMv4t and later, and at least on A15 both should perform
exactly the same (both have exec 1 uop 1, type I).

2013-05-31-char-shift-crash.ll is a bitcode version of the above bug
16178 repro.

fast-isel-ext.ll tests all sext/zext combinations that ARM FastISel
should now handle.

Note that my ARM FastISel enabling patch was reverted due to a separate
failure when dealing with MCJIT, I'll fix this second failure and then
turn FastISel on again for non-iOS ARM targets.

I've tested "make check-all" on my x86 box, and "lnt test-suite" on A15
hardware.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183551 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 20:10:37 +00:00
Benjamin Kramer
1983a4cbf1 R600: Don't compare iterators of different maps. 
Found be libstdc's debug mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183549 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 19:59:34 +00:00
Eli Bendersky
1de1410bd2 Add explicit link targets to some headers in LangRef.rst 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183548 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 19:40:08 +00:00
Manman Ren
eda4b8e674 No functionality change. 
Constify a few member functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183546 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 18:53:29 +00:00
Quentin Colombet
fcca6c690c Teach AsmPrinter how to print odd constants. 
Fix an assertion when the compiler encounters big constants whose bit width is
not a multiple of 64-bits.
Although clang would never generate something like this, the backend should be
able to handle any legal IR.

<rdar://problem/13363576>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183544 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 18:36:03 +00:00
Manman Ren
576d49a775 DIBuilder: No functionality change. 
Use the correct DIType when creating types in DIBuilder.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183543 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 18:35:53 +00:00
Benjamin Kramer
2e0cebd881 Vincent says the element is at most once in the vector, so we don't need a full std::remove. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183541 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 18:18:12 +00:00
Rafael Espindola
149d1a1894 Use isxdigit. 
Thanks to Benjamin Kramer for the suggestion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183540 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 18:05:03 +00:00
Rafael Espindola
814b52710a Make operator== non-member for greater symmetry. 
Thanks to David Blaikie for the suggestion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183539 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 18:00:04 +00:00
Roman Divacky
6ca5fd3f30 Fix a typo in asm string of BP* family of instructions. With this fix 
I am able to compile/assemble/link/run /bin/echo from FreeBSD.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183537 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 17:46:57 +00:00
Rui Ueyama
2e2630b462 [Object/COFF] BaseOfData field should be absent in PE32+. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183534 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 16:58:30 +00:00
Rafael Espindola
62ed8d3e35 Support OpenBSD's native frame protection conventions. 
OpenBSD's stack smashing protection differs slightly from other
platforms:

  1. The smash handler function is "__stack_smash_handler(const char
     *funcname)" instead of "__stack_chk_fail(void)".

  2. There's a hidden "long __guard_local" object that gets linked
     into each executable and DSO.

Patch by Matthew Dempsky.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183533 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 16:35:57 +00:00
Benjamin Kramer
47b0c0a9a0 R600: Fix a potential iterator invalidation issue. 
As a bonus this reduces the loop from O(n^2) to O(n).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183532 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 16:13:49 +00:00
Vincent Lejeune
74f03455e5 R600: Remove an extra break in R600OptimizeVectorRegisters.cpp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183528 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 15:44:53 +00:00
Alexey Samsonov
b6564648a5 [llvm-symbolizer] rewrite r183213 in a more clear way 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183526 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 15:25:27 +00:00
Benjamin Kramer
a77376dae1 BitVector: Do the right thing in all() when Size is a multiple of BITWORD_SIZE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183525 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 15:14:31 +00:00
Benjamin Kramer
597253da97 Optimize BitVector::all(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183521 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 14:14:38 +00:00
Benjamin Kramer
041399aad5 Fold variable that's only used in assert into the assert. 
Avoids unused variable warnings in Release builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183512 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 11:23:35 +00:00
Bill Wendling
ab5ad9fe50 Add a script to help us create source tar balls for the release. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183509 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 11:15:30 +00:00
Bill Wendling
451ee21d14 Use proper exit code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183508 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 11:14:37 +00:00
Duncan Sands
f4a66d2005 Correct wrong register in this example, pointed out by Baoshan Pang. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183495 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 08:30:55 +00:00
Bill Wendling
80ada583f3 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183494 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 07:55:53 +00:00
Bill Wendling
41e632d9e1 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183493 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 07:04:14 +00:00
Bill Wendling
ed8b5b55a4 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183492 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 06:30:15 +00:00
Bill Wendling
637eab6a3b Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183491 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 06:26:43 +00:00
Bill Wendling
54a56fad36 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183490 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 06:19:56 +00:00
Michael Gottesman
9eb856bc29 [objc-arc] Ensure that the cfg path count does not overflow when we multiply TopDownPathCount/BottomUpPathCount. 
rdar://12480535

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183489 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 06:16:49 +00:00
Bill Wendling
57148c166a Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183488 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 05:54:19 +00:00
Bill Wendling
4393f48c03 Don't cache the instruction info and register info objects. 
These objects are internal to the TargetMachine object and may change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183485 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 05:00:11 +00:00
Manman Ren
37bfb18f8f DIBuilder: No functionality change. 
Use the correct DIType when creating vector types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183484 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 03:13:46 +00:00
Arnold Schwaighofer
c6752d5565 ARM sched model: Use the right resources for DIV 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183477 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 01:16:15 +00:00
Arnold Schwaighofer
873ff29514 ARM sched model: Add VFP div instruction on Swift 
Reapply 183271.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183472 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 01:10:36 +00:00
Arnold Schwaighofer
0efc78257b CodeGenSchedule: Use resize instead of copying a vector 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183465 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-07 00:04:30 +00:00