Chad Rosier
6e99a8cb37
[arm fast-isel] Appease the machine verifier by using the proper register
...
classes. The vast majority of the remaining issues are due to uses of
invalid registers, which are defined by getRegForValue(). Those will be
a little more challenging to cleanup.
rdar://12719844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168735 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27 22:29:43 +00:00
Chad Rosier
b1146a242c
[arm fast-isel] Appease the machine verifier by using the proper register
...
classes.
rdar://12719844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168733 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27 22:12:11 +00:00
Chad Rosier
ac3158b571
[arm fast-isel] Appease the machine verifier by using the proper register
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classes. Also a bit of cleanup.
rdar://12719844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168728 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27 21:46:46 +00:00
Chad Rosier
fc17ddd889
[arm fast-isel] Appease the machine verifier by using the proper register
...
classes. The associated test case still doesn't pass, but it does have far
fewer issues.
rdar://12719844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168657 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27 01:06:49 +00:00
Chad Rosier
b3235b128f
Revert r167620; this can be implemented using an existing CL option.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167622 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09 18:25:27 +00:00
Chad Rosier
d054eda441
Add support for -mstrict-align compiler option for ARM targets.
...
rdar://12340498
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167620 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09 17:29:38 +00:00
Chad Rosier
6aa6e5a285
[arm fast-isel] Appease the machine verifier by using the proper register
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classes. For my test case the number of errors drop from 356 to 21.
Part of rdar://12594152
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167508 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07 00:13:01 +00:00
Bill Wendling
8f47fc8f00
When a block ends in an indirect branch, add its successors to the machine basic block.
...
The CFG of the machine function needs to know that the targets of the indirect
branch are successors to the indirect branch.
<rdar://problem/12529625>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166448 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-22 23:30:04 +00:00
Bill Wendling
3e2d76c946
Use the attribute enums to query if a parameter has an attribute.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165550 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09 21:38:14 +00:00
Micah Villmow
3574eca1b0
Move TargetData to DataLayout.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08 16:38:25 +00:00
Bill Wendling
847d165459
Add methods which query for the specific attribute instead of using the
...
enums. This allows for better encapsulation of the Attributes class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165132 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03 17:54:26 +00:00
Sylvestre Ledru
94c22716d6
Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27 10:14:43 +00:00
Sylvestre Ledru
7e2c793a2b
Fix a typo 'iff' => 'if'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164767 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27 09:59:43 +00:00
Jush Lu
8f50647662
[arm-fast-isel] Add support for ELF PIC.
...
This is a preliminary step towards ELF support; currently ARMFastISel hasn't
been used for ELF object files yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164759 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27 05:21:41 +00:00
Chad Rosier
e5e674ba11
[fast-isel] Fallback to SelectionDAG isel if we require strict alignment for
...
non-aligned i32 loads/stores.
rdar://12304911
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164381 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21 16:58:35 +00:00
Chad Rosier
d70c98e884
[fast-isel] Fallback to SelectionDAG isel if we require strict alignment for
...
non-halfword-aligned i16 loads/stores.
rdar://12304911
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164345 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21 00:41:42 +00:00
Nadav Rotem
e757640df0
Fix a few old-GCC warnings. No functional change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163309 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 11:13:55 +00:00
Jush Lu
c4dc2490c4
[arm-fast-isel] Add support for ARM PIC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162823 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 02:41:21 +00:00
Jakob Stoklund Olesen
0745b649ed
Fix call instruction operands in ARMFastISel.
...
The ARM BL and BLX instructions don't have predicate operands, but the
thumb variants tBL and tBLX do.
The argument registers should be added as implicit uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162593 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 20:52:46 +00:00
Craig Topper
35fc62bf70
Remove virtual from many methods. These methods replace methods in the base class, but the base class methods aren't virtual so it just increased call overhead.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162178 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-18 21:38:45 +00:00
Jush Lu
2ff4e9d5af
[arm-fast-isel] Add support for fastcc.
...
Without fastcc support, the caller just falls through to CallingConv::C
for fastcc, but callee still uses fastcc, this inconsistency of calling
convention is a problem, and fastcc support can fix it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162013 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-16 05:15:53 +00:00
Bob Wilson
d49edb7ab0
Fall back to selection DAG isel for calls to builtin functions.
...
Fast isel doesn't currently have support for translating builtin function
calls to target instructions. For embedded environments where the library
functions are not available, this is a matter of correctness and not
just optimization. Most of this patch is just arranging to make the
TargetLibraryInfo available in fast isel. <rdar://problem/12008746>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161232 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 04:06:28 +00:00
Jush Lu
2946549a28
[arm-fast-isel] Add support for shl, lshr, and ashr.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161230 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 02:37:48 +00:00
Eric Christopher
e94ac8871a
Add support for the ARM GHC calling convention, this patch was in 3.0,
...
but somehow managed to be dropped later.
Patch by Karel Gardas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 00:05:53 +00:00
Jush Lu
ee649839a2
[arm-fast-isel] Add support for vararg function calls.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160500 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-19 09:49:00 +00:00
NAKAMURA Takumi
bd985efa99
Revert r159804, "[arm-fast-isel] Add support for vararg function calls."
...
It broke LLVM :: CodeGen/Thumb2/large-call.ll on several hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159817 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06 11:12:44 +00:00
Jush Lu
a8c4d739f2
[arm-fast-isel] Add support for vararg function calls.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159804 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06 03:02:37 +00:00
Jush Lu
efc967e044
Cleanup whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158443 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-14 06:08:19 +00:00
Chad Rosier
49d6fc02ef
[arm-fast-isel] Add support for -arm-long-calls.
...
Patch by Jush Lu <jush.msn@gmail.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158368 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-12 19:25:13 +00:00
Bill Wendling
ad5c880892
Re-enable the CMN instruction.
...
We turned off the CMN instruction because it had semantics which we weren't
getting correct. If we are comparing with an immediate, then it's okay to use
the CMN instruction.
<rdar://problem/7569620>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158302 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-11 08:07:26 +00:00
Chad Rosier
bbff4ee92d
[arm-fast-isel] Fix handling of the frameaddress intrinsic. If depth is 0
...
then DestReg is undefined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157840 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-01 21:12:31 +00:00
Chad Rosier
ada759d5fa
[arm-fast-isel] Add support for the llvm.frameaddress() intrinsic.
...
Patch by Jush Lu <jush.msn@gmail.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157696 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 17:23:22 +00:00
Chad Rosier
1c8fccbc12
[arm-fast-isel] Add support for non-global callee.
...
Patch by Jush Lu <jush.msn@gmail.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157336 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-23 18:38:57 +00:00
Chad Rosier
226ddf5278
[fast-isel] Add support for selecting @llvm.trap().
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 21:33:49 +00:00
Chad Rosier
2b3b335f2d
[fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. Minor cleanup.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156632 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 19:40:25 +00:00
Chad Rosier
2a2e9d54e9
[fast-isel] Cleaner fix for when we're unable to handle a non-double multi-reg
...
retval. Hoists check before emitting the call to avoid unnecessary work.
rdar://11430407
PR12796
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156628 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 18:51:55 +00:00
Chad Rosier
2f6ae41f14
[fast-isel] Rather then assert (or segfault in a non-asserts build), fall back
...
to selection DAG isel if we're unable to handle a non-double multi-reg retval.
rdar://11430407
PR12796
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156622 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 17:41:06 +00:00
Chad Rosier
f4bd21c256
The return type is an unsigned, not a bool.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156621 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11 16:41:38 +00:00
Craig Topper
420761a0f1
Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20 07:30:17 +00:00
Jim Grosbach
d4f020a3af
Tidy up. 80 columns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-06 23:43:50 +00:00
Jakob Stoklund Olesen
f16936e592
Deduplicate ARM call-related instructions.
...
We had special instructions for iOS because r9 is call-clobbered, but
that is represented dynamically by the register mask operands now, so
there is no need for the pseudo-instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154144 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-06 00:04:58 +00:00
Craig Topper
c89c744b69
Remove unnecessary llvm:: qualifications
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153500 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27 07:21:54 +00:00
Craig Topper
0e5233a9e5
Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.h
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153422 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-26 00:45:15 +00:00
Bill Wendling
5aeff3171c
Check if we can handle the arguments of a call (and therefore the call) in
...
fast-isel before emitting code. If the program bails after code was emitted,
then it could lead to the stack being adjusted more than once (two
CALLSEQ_BEGINs emitted) but being adjuste back only once after the call. This
leads to general badness and gnashing of teeth.
<rdar://problem/11050630>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152959 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16 23:11:07 +00:00
Chad Rosier
0ac754f6f4
[fast-isel] Address Eli's comments for r152847. Specifically, add a test case
...
and still allow immediate encoding, just not with cmn.
rdar://11038907
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152869 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15 22:54:20 +00:00
Chad Rosier
530b19b702
[fast-isel] Don't try to encode LONG_MIN using cmn instructions.
...
rdar://11038907
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152847 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15 21:40:23 +00:00
Chad Rosier
44c98b7114
[fast-isel] ARMEmitCmp generates FMSTAT, which transfers the floating-point
...
condition flags to CPSR. This allows us to simplify SelectCmp.
Patch by Zonr Chang <zonr.xchg@gmail.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152243 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 20:59:26 +00:00
Lang Hames
4f92b5e616
Split fpscr into two registers: FPSCR and FPSCR_NZCV.
...
The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152076 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 00:19:55 +00:00
Jim Grosbach
e751c0069a
ARM use the right opcode for FP<->Integer move in fast-isel.
...
rdar://10965031
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151850 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 22:47:09 +00:00
Jakob Stoklund Olesen
c54f634886
Switch ARM target to register masks.
...
I'll let the buildbots determine the compile time improvements from this
change, but 464.h264ref has 5% faster codegen at -O2.
This patch does cause some assembly changes. Branch folding can make
different decisions about calls with dead return values.
CriticalAntiDepBreaker may choose different registers because its
liveness tracking is affected. MachineCopyPropagation may sometimes
leave a dead copy behind.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151331 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24 01:19:29 +00:00
Craig Topper
44d23825d6
Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22 05:59:10 +00:00
Chad Rosier
b8703fe265
[fast-isel] Add support for returning non-legal types with no sign- or zero-
...
entend flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150774 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17 01:21:28 +00:00
Chad Rosier
a69feb0f33
Remove unnecessary assignment to temporary, ResultReg.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150737 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16 22:45:33 +00:00
Chad Rosier
40d552e0be
Add braces to if clause to make symmetric with associate else clause.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150591 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15 17:36:21 +00:00
Chad Rosier
92fd017364
Use a temporary variable, rather then a series of redundant calls.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150536 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-15 00:23:55 +00:00
Chad Rosier
5793a6586d
Remove unnecessary assignment to temporary, ResultReg.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150520 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14 22:29:48 +00:00
Chad Rosier
743e19983e
[fast-isel] Add support for SUBs with non-legal types.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150047 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 02:45:44 +00:00
Chad Rosier
6fde875621
[fast-isel] Add support for ORs with non-legal types.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150045 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 02:29:21 +00:00
Chad Rosier
60c8fa6bb9
[fast-isel] Add support for indirect branches.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150014 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-07 23:56:08 +00:00
Craig Topper
bc2198133a
Convert assert(0) to llvm_unreachable
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-07 02:50:20 +00:00
Chad Rosier
3901c3e750
[fast-isel] Add support for ADDs with non-legal types.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149934 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-06 23:50:07 +00:00
Duncan Sands
5b8a1db7ea
Persuade GCC that there is nothing worth warning about here (there isn't).
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149834 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 14:20:11 +00:00
Chad Rosier
769422f0fc
[fast-isel] Add support for URem.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149716 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 21:23:45 +00:00
Chad Rosier
ae46a3362d
[fast-isel] Rename isZExt to isSigned. No functional change intended.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149714 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 21:14:11 +00:00
Chad Rosier
7ccb30b596
[fast-isel] Add support for UDIV.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 21:07:27 +00:00
Chad Rosier
ee8901c08f
[fast-isel] Add support for FPToUI. Also add test cases for FPToSI.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149706 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 20:27:51 +00:00
Chad Rosier
36b7beb429
[fast-isel] Add support for selecting UIToFP.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149704 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 19:42:52 +00:00
David Blaikie
4d6ccb5f68
More dead code removal (using -Wunreachable-code)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 21:51:11 +00:00
Eric Christopher
fae699a580
Fix assert.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147966 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-11 20:55:27 +00:00
Jakob Stoklund Olesen
8f37a2422e
Match SelectionDAG logic for enabling movt.
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Darwin doesn't do static, and ELF targets only support static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147740 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07 20:49:15 +00:00
Jakob Stoklund Olesen
4964ba01f9
Use getRegForValue() to materialize the address of ARM globals.
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This enables basic local CSE, giving us 20% smaller code for
consumer-typeset in -O0 builds.
<rdar://problem/10658692>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147720 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07 04:07:22 +00:00
Jakob Stoklund Olesen
45ca7c6336
Use movw+movt in ARMFastISel::ARMMaterializeGV.
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This eliminates a lot of constant pool entries for -O0 builds of code
with many global variable accesses.
This speeds up -O0 codegen of consumer-typeset by 2x because the
constant island pass no longer has to look at thousands of constant pool
entries.
<rdar://problem/10629774>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07 01:47:05 +00:00
Evan Cheng
afff941211
ARM target code clean up. Check for iOS, not Darwin where it makes sense.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 18:26:50 +00:00
Chad Rosier
6762f8f302
VFP2 is required for FP loads. Noticed by inspection.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 17:55:03 +00:00
Chad Rosier
64ac91b4b6
Tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146568 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 17:32:02 +00:00
Chad Rosier
404ed3c223
Fix 80-column violation and extraneous brackets.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146566 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 17:26:05 +00:00
Evan Cheng
ddfd1377d2
- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
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to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
prevent IT blocks from being broken apart.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146542 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 02:11:42 +00:00
Chad Rosier
8a9bce978f
[fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular
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load and then move the result from a GPR to a FPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 19:22:14 +00:00
Evan Cheng
5a96b3dad2
Add bundle aware API for querying instruction properties and switch the code
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generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 07:15:52 +00:00
Chad Rosier
ed42c5f778
[arm-fast-isel] Doublewords only require word-alignment.
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rdar://10528060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145891 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 01:44:17 +00:00
Bob Wilson
6ce2deacef
Fix 80-column issues.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145783 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-04 00:52:23 +00:00
Chad Rosier
9eff1e33f6
[arm-fast-isel] Unaligned stores of floats require special care.
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rdar://10510150
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145742 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-03 02:21:57 +00:00
Nick Lewycky
8a8d479214
Move global variables in TargetMachine into new TargetOptions class. As an API
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change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.
One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 22:16:29 +00:00
Chad Rosier
b74c865841
[arm-fast-isel] After promoting a function parameter be sure to update the
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argument value type. Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145701 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 20:25:18 +00:00
Duncan Sands
4c0c5451c7
Silence wrong warnings from GCC about variables possibly being used
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uninitialized: GCC doesn't understand that the variables are only used
if !UseImm, in which case they have been initialized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145239 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-28 10:31:27 +00:00
Chad Rosier
424fe0e422
Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144959 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-18 01:17:34 +00:00
Chad Rosier
944d82ba06
Add TODO comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144920 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 21:46:13 +00:00
Chad Rosier
2fb82ce75d
Dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 07:24:49 +00:00
Chad Rosier
3bdb3c9b51
Don't unconditionally set the kill flag.
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rdar://10456186
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144872 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 01:16:53 +00:00
Chad Rosier
508a1f4db1
Check to make sure we can select the instruction before trying to put the
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operands into a register. Otherwise, we may materialize dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144805 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 18:39:44 +00:00
Chad Rosier
f56c60b571
Add FIXME comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144743 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 00:32:20 +00:00
Jay Foad
d9190c0f14
Remove some unnecessary includes of PseudoSourceValue.h.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144631 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 07:24:32 +00:00
Chad Rosier
2c42b8c912
Supporting inline memmove isn't going to be worthwhile. The only way to avoid
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violating a dependency is to emit all loads prior to stores. This would likely
cause a great deal of spillage offsetting any potential gains.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144585 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:04:09 +00:00
Chad Rosier
909cb4f2f2
Add support for inlining small memcpys.
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rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144578 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 22:46:17 +00:00
Chad Rosier
e489af8dce
Fix a performance regression from r144565. Positive offsets were being lowered
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into registers, rather then encoded directly in the load/store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144576 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 22:34:48 +00:00
Chad Rosier
57b2997966
Add support for Thumb load/stores with negative offsets.
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rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144565 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 20:22:27 +00:00
Chad Rosier
dc9205d9c2
Add support for ARM halfword load/stores and signed byte loads with negative
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offsets.
rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 04:09:28 +00:00
Chad Rosier
9eb674880b
The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144494 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 09:44:21 +00:00
Chad Rosier
a517ab155b
Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144492 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 05:14:43 +00:00
Chad Rosier
5be833de76
Fix comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144490 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13 04:25:02 +00:00