Commit Graph

1768 Commits

Author SHA1 Message Date
Akira Hatanaka
434c0bd2a5 [mips] Implement MipsTargetMachine::getInstrItineraryData().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186227 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-12 23:33:22 +00:00
Akira Hatanaka
ae24f7d3c6 [mips] Add instruction itinerary classes for mult, seb and slt instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186222 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-12 22:43:20 +00:00
Vladimir Medic
dd51a0c1e0 Add support for Mips break and syscall insructions. The corresponding test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186151 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-12 09:25:35 +00:00
Vladimir Medic
296c1534b4 Reverting commit r185999 due to buildboot failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186000 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-10 12:26:26 +00:00
Vladimir Medic
2ec5933eae Add support for Mips break and syscall insructions. The corresponding test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185999 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-10 10:18:10 +00:00
Jakob Stoklund Olesen
f349a6e9e6 Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185625 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 13:54:20 +00:00
Craig Topper
6227d5c690 Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185606 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 01:31:24 +00:00
Jakob Stoklund Olesen
c93822901a Revert r185595-185596 which broke buildbots.
Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185600 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 00:26:30 +00:00
Jakob Stoklund Olesen
62204220e1 Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185596 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 23:56:31 +00:00
Craig Topper
365ef0b197 Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185540 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 15:07:05 +00:00
Akira Hatanaka
a66aacf6d7 [mips] Add new InstrItinClasses for move from/to coprocessor instructions and
floating point loads and stores.

No changes in functionality.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185399 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-02 00:00:02 +00:00
Akira Hatanaka
5112243aec [mips] Reverse the order of source operands of shift and rotate instructions that
have three register operands.

No intended functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185376 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 20:39:53 +00:00
Akira Hatanaka
db8e0bbedb [mips] Increase the number of floating point control registers available to 32.
Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185373 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 20:31:44 +00:00
Chad Rosier
096c0a0331 [Mips Disassembler] Have the DecodeCCRRegisterClass function use the getReg
function to lookup the proper tablegen'ed register enumeration.  Previously,
it was using the encoded value directly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185026 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-26 22:23:32 +00:00
Akira Hatanaka
842cfc91f2 [mips] Do not emit ".option pic0" if target is mips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185012 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-26 19:08:49 +00:00
Akira Hatanaka
9a308df027 [mips] Improve code generation for constant multiplication using shifts, adds and
subs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185011 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-26 18:48:17 +00:00
Vladimir Medic
90b1086b93 This patch introduces RegisterOperand class into Mips FPU instruction definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184716 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 10:05:34 +00:00
Chad Rosier
5b3fca50a0 The getRegForInlineAsmConstraint function should only accept MVT value types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-22 18:37:38 +00:00
Vladimir Medic
7231625f75 Optimize register parsing for MipsAsmParser. Allow symbolic aliases for FPU registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184411 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-20 11:21:49 +00:00
Bill Wendling
ba54bca472 Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184360 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-19 21:36:55 +00:00
Vladimir Medic
dd5fe2ffc6 The RenderMethod field in RegisterOperand class sets the name of the method on the target specific operand to call to add the target specific operand to an MCInst. This patch defines RenderMethod for mips RegisterOperand classes and removes redundant code from MipsAsmParser.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184292 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-19 10:14:36 +00:00
Jack Carter
571dd98ea4 Mips ELF: Mark object file as ABI compliant
When producing objects that are abi compliant we are 
marking neither the object file nor the assembly file
correctly and thus generate warnings. 

We need to set the EF_CPIC flag in the ELF header when
generating direct object.

Note that the warning is only generated when compiling without PIC.

When compiling with clang the warning will be suppressed by supplying:

 -Wa,-mno-shared -Wa,-call_nonpic

Also the following directive should also be added:

	.option	pic0

when compiling without PIC,  This eliminates the need for supplying:

  -mno-shared -call_nonpic

on the assembler command line.

Patch by Douglas Gilmore


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-18 19:47:15 +00:00
Bill Wendling
99cb622041 Use pointers to the MCAsmInfo and MCRegInfo.
Someone may want to do something crazy, like replace these objects if they
change or something.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184175 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-18 07:20:20 +00:00
David Blaikie
0187e7a9ba DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-16 20:34:27 +00:00
Benjamin Kramer
90cd06e90b Mips: Remove global set.
Backends shouldn't retain any global state. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183927 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-13 19:06:52 +00:00
Akira Hatanaka
0001acc13c Fix CMakeLists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183804 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 22:36:30 +00:00
Akira Hatanaka
45137f954f [mips] Add an IR transformation pass that optimizes calls to sqrt.
The pass emits a call to sqrt that has attribute "read-none". This call will be
converted to an ISD::FSQRT node during DAG construction, which will turn into
a mips native sqrt instruction.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183802 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 22:21:44 +00:00
Akira Hatanaka
4cef3d8181 [mips] Use function TargetInstrInfo::getRegClass.
No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183767 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-11 18:48:16 +00:00
Reed Kotler
b0ee97a366 Fix a regression I introduced when I expanded the complex pseudos in
the Mips16 port. A few of the psuedos could either take signed
or unsigned arguments and I did not distinguish the case and improperly
rejected some valid cases that the assembler had previously accepted
when they were pure pseudos that expanded as assembly instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183633 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-09 23:23:46 +00:00
Akira Hatanaka
7462a875d9 [mips] Use a helper function which compares the size of the source and
destination operands of an instruction.

No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183596 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-08 00:14:54 +00:00
Bill Wendling
41e632d9e1 Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183493 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 07:04:14 +00:00
Bill Wendling
6a2e7ac0b6 Cache the TargetLowering info object as a pointer.
Caching it as a pointer allows us to reset it if the TargetMachine object
changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183361 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 00:43:09 +00:00
Akira Hatanaka
8270e68c56 [mips] brcond + setgt/setugt instruction selection patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183334 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 19:49:55 +00:00
Vladimir Medic
164de54391 Test commit for user vmedic, to verify commit access. One line of comment is added to MipsAsmParser.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183215 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 08:28:53 +00:00
Ahmed Bougacha
23ed37a6b7 Make SubRegIndex size mandatory, following r183020.
This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-31 23:45:26 +00:00
Akira Hatanaka
affed7e11d [mips] Big-endian code generation for atomic instructions.
Patch by Jyun-Yan You.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-31 03:25:44 +00:00
Andrew Trick
6e0b2a0cb0 Order CALLSEQ_START and CALLSEQ_END nodes.
Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.

Patch by Xiaoyi Guo!

This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182885 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-29 22:03:55 +00:00
Jack Carter
c57905ef4d Mips assembler: Improve set register alias handling
This patch solves the problem of numeric register values not being accepted:

../set_alias.s:1:11: error: expected valid expression after comma
        .set    r4,$4
                    ^
The parsing of .set directive is changed and handling of symbols in code 
as well to enable this feature. 

The test example is added.

Patch by Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182807 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-28 22:21:05 +00:00
Rafael Espindola
078bdc6cbb Make helper functions static.
And remove header and cpp file that are empty after that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182746 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-27 22:34:59 +00:00
Andrew Trick
ac6d9bec67 Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-25 02:42:55 +00:00
Michael J. Spencer
c6af2432c8 Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182680 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-24 22:23:49 +00:00
Benjamin Kramer
49a6a8d8f2 Remove the Copied parameter from MemoryObject::readBytes.
There was exactly one caller using this API right, the others were relying on
specific behavior of the default implementation. Since it's too hard to use it
right just remove it and standardize on the default behavior.

Defines away PR16132.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182636 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-24 10:54:58 +00:00
Reed Kotler
6c1301ba8c Mips16 does not use register scavenger from TargetRegisterInfo. It allocates
a RegScavenger object on it's own.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182430 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21 22:06:02 +00:00
Akira Hatanaka
2591b5c6c3 [mips] Rename option to make it compatible with gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182397 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21 17:17:59 +00:00
Akira Hatanaka
1d4d32398d [mips] Add instruction selection patterns for blez and bgez.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182396 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21 17:13:47 +00:00
Reed Kotler
bf00bf9ad2 Add some additional functions to the list of helper functions for
pic calls. These need to be there so we don't try and use helper
functions when we call those.

As part of this, make sure that we properly exclude helper functions in pic
mode when indirect calls are involved.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182343 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21 00:50:30 +00:00
Akira Hatanaka
1aeb13bd9c [mips] Add (setne $lhs, 0) instruction selection pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182307 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 18:18:07 +00:00
Akira Hatanaka
f894199a14 [mips] Trap on integer division by zero.
By default, a teq instruction is inserted after integer divide. No divide-by-zero
checks are performed if option "-mnocheck-zero-division" is used.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182306 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 18:07:43 +00:00
Matt Arsenault
225ed7069c Add LLVMContext argument to getSetCCResultType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-18 00:21:46 +00:00
Akira Hatanaka
ae7e7cb3d3 [mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr).
Previously, three instructions were needed:

trunc.w.s $f0, $f2
mfc1 $4, $f0
sw $4, 0($2)

Now we need only two:

trunc.w.s $f0, $f2
swc1 $f0, 0($2)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182053 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16 21:17:15 +00:00