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Commit Graph

2048 Commits

Author SHA1 Message Date
Nate Begeman
918f8e4ab0 Add the last of the SemaChecking-gen code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105929 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-14 05:17:23 +00:00
Nate Begeman
d72c900152 Add a helping of comments
Add code for generating bits of semachecking


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105907 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-13 04:47:03 +00:00
Chris Lattner
5ca96988b0 declare a class with 'class' instead of struct to avoid tag mismatch
warnings, and don't shift by a bool.  Patch by Rizky Herucakra!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105886 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12 15:46:56 +00:00
Nate Begeman
cc3c41a9c3 Add generic vector support for bitselect & element byteswap
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105874 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12 03:09:49 +00:00
Bruno Cardoso Lopes
c902a59f4c More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm)
Introduce the VEX_X field


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-11 23:50:47 +00:00
Bob Wilson
1a913ed178 Add instruction encoding for the Neon VMOV immediate instruction. This changes
the machine instruction representation of the immediate value to be encoded
into an integer with similar fields as the actual VMOV instruction.  This makes
things easier for the disassembler, since it can just stuff the bits into the
immediate operand, but harder for the asm printer since it has to decode the
value to be printed.  Testcase for the encoding will follow later when MC has
more support for ARM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105836 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-11 21:34:50 +00:00
Nate Begeman
d6645dd4fe Add support for polynomial type, for polynomial multiply
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105792 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-10 18:06:07 +00:00
Bruno Cardoso Lopes
ee65db3add Teach tablegen to allow "let" expressions inside multiclasses,
providing more ways to factor out commonality from the records.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105776 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-10 02:42:59 +00:00
Nate Begeman
4b425a8caa NEON support for _lane ops, and multiplies by scalar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105769 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-10 00:16:56 +00:00
Nate Begeman
f50551eb08 Further refine types for operations which take scalars.
This will be used primarily by NEON shift intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105733 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09 18:02:26 +00:00
Eric Christopher
622dffde86 How about ULL...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105726 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09 16:16:48 +00:00
Nate Begeman
007afe4b4b Specialize I-Class instructions better so that we have less work to do in codegen.
Parenthesize macro args


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105682 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09 05:11:55 +00:00
Nate Begeman
6c060dbf84 Handle instructions which need to be #defines for the purpose of capturing constant arguments
Handle extract hi/lo with common code


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105666 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-09 01:09:00 +00:00
Bruno Cardoso Lopes
99405df044 Reapply r105521, this time appending "LLU" to 64 bit
immediates to avoid breaking the build.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 22:51:23 +00:00
Nate Begeman
96ec22d683 Fix a valgrind error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105600 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 07:11:17 +00:00
Nate Begeman
5638783276 Refine BuiltinsARM.def types a bit, we should do a better job of this to save some c++ code in CGBuiltins.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105598 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 06:01:16 +00:00
Nate Begeman
900f4674c1 ARM NEON:
fix vcvt naming
handle vdup, vcombine with generic vector code


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105588 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 00:14:42 +00:00
Nate Begeman
b0a4e4554e clang codegen support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-07 16:00:37 +00:00
Chris Lattner
1087f54ddb revert r105521, which is breaking the buildbots with stuff like this:
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105524 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-05 04:17:30 +00:00
Bruno Cardoso Lopes
3eca98bb3a Initial AVX support for some instructions. No patterns matched
yet, only assembly encoding support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105521 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-05 03:53:24 +00:00
Bruno Cardoso Lopes
270562b3d4 Teach tablegen to support 'defm' inside multiclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105519 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-05 02:11:52 +00:00
Nate Begeman
9e584b37b0 Handle multi-vector returns and args.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105496 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04 22:53:30 +00:00
Nate Begeman
7c21f747c7 Additional fixes to BuiltinsARM.def generator, on to clang codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105488 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04 21:36:00 +00:00
Nate Begeman
92f98af9fb Progress on generating BuiltinsARM.def, still some duplicates to work out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105461 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04 07:11:25 +00:00
Nate Begeman
73cef3e9b1 BuiltinsARM.def emitter, still needs a substantial bit of tweaking to lighten the load on clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105456 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04 01:26:15 +00:00
Nate Begeman
a8979a0e7b Mangle __builtin_neon_* names appropriately.
Add skeleton of support for emitting the list of prototypes for BuiltinsARM.def


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105443 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04 00:21:41 +00:00
Nate Begeman
3861e74490 Add some additional capabilities to the neon emitter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105416 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03 21:35:22 +00:00
Dale Johannesen
51e28e6348 Early implementation of tail call for ARM.
A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105413 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03 21:09:53 +00:00
Nate Begeman
162d3ba464 arm_neon.h now makes it through clang and generates appropriate code for those functions which can use
generic vector operators rather than __builtin_neon_*


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105380 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03 04:04:09 +00:00
Nate Begeman
7c8c8830a9 arm_neon.h emitter now mostly complete for the purposes of initial testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105349 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 21:53:00 +00:00
Duncan Sands
8dbbacedcd Pacify recent gcc: remove a pointless const qualifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105318 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 08:37:30 +00:00
Nate Begeman
e66aab553c Checkpoint; handle 'int' and 'void' correctly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105316 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 07:14:28 +00:00
Nate Begeman
af905efc61 Emit full function prototypes. Definitions & typedefs to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105315 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 06:17:19 +00:00
Nate Begeman
22237771d8 Checkpoint arm_neon.h generation with tablegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105307 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02 00:34:55 +00:00
Sean Hunt
891f27380c Fix comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105297 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-01 23:29:39 +00:00
Sean Hunt
c10a62b0d5 Allow for creation of clang DeclNodes tables.
The StmtNodes generator has been generalized to allow for the
creation of DeclNodes tables as well, and another emitter was
added for DeclContexts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105164 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-30 07:21:42 +00:00
Jakob Stoklund Olesen
7c9a6e3284 Emit TargetRegisterInfo::composeSubRegIndices().
Also verify that all subregister indices compose unambiguously.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 23:48:31 +00:00
Nate Begeman
e8f0349439 Comment out some code in prep for actual .td file checkpoint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104927 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 02:19:08 +00:00
Eli Friedman
a4fda2c757 Fix build breakage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104912 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 01:15:28 +00:00
Nate Begeman
5ddb087f7f Add support to tablegen for auto-generating arm_neon.h from a tablegen description
of the intrinsics.  The goal is to auto-generate both support for GCC-style (vector)
and ARM-style (struct of vector) intrinsics.

This is work in progress, but will be completed soon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104910 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 01:08:32 +00:00
Dan Gohman
9d2cbffed0 Simplify raw_ostream usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104874 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 19:48:08 +00:00
Dan Gohman
098d3a41e1 Minor code simplification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104845 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 16:25:05 +00:00
Daniel Dunbar
368a456503 AsmMatcher: Ensure classes are totally ordered, so we can std::sort them reliably.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104806 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 05:31:32 +00:00
Jakob Stoklund Olesen
6f0ff1d578 Check that inherited subregisters all have a direct SubRegIndex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104755 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 22:15:07 +00:00
Jakob Stoklund Olesen
160a3bf74d Add StringRef::compare_numeric and use it to sort TableGen register records.
This means that our Registers are now ordered R7, R8, R9, R10, R12, ...
Not R1, R10, R11, R12, R2, R3, ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 21:47:28 +00:00
Jakob Stoklund Olesen
f86a619314 Suppress emmission of empty subreg/superreg/alias sets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104741 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 21:35:55 +00:00
Jakob Stoklund Olesen
ca561ffcf3 Replace the SubRegSet tablegen class with a less error-prone mechanism.
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 17:27:12 +00:00
Jakob Stoklund Olesen
b555609e73 Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."
This reverts commit 104654.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 01:21:14 +00:00
Jakob Stoklund Olesen
6a45d681e5 Replace the SubRegSet tablegen class with a less error-prone mechanism.
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 00:28:19 +00:00
Jakob Stoklund Olesen
76f0ad7bf5 Drop the SuperregHashTable. It is essentially the same as SubregHashTable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104650 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 23:43:18 +00:00
Jakob Stoklund Olesen
1fc8e759a7 Print symbolic SubRegIndex names on machine operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104628 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 19:49:38 +00:00
Jakob Stoklund Olesen
48d0c163fb Ignore NumberHack and give each SubRegIndex instance a unique enum value instead.
This passes lit tests, but I'll give it a go through the buildbots to smoke out
any remaining places that depend on the old SubRegIndex numbering.

Then I'll remove NumberHack entirely.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104615 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 17:21:04 +00:00
Jakob Stoklund Olesen
33276d95ef Switch SubRegSet to using symbolic SubRegIndices
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 23:03:18 +00:00
Chris Lattner
ec5a0b336a diaggroup categories should take precedence over diag-specific groups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104567 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 21:55:47 +00:00
Jakob Stoklund Olesen
09bc029865 Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 21:46:58 +00:00
Jakob Stoklund Olesen
73ea7bf450 Add the SubRegIndex TableGen class.
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104492 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 14:48:12 +00:00
Daniel Dunbar
54ddf3d9c7 tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104452 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 21:02:29 +00:00
Daniel Dunbar
4072886a69 tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor
it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104270 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:20:32 +00:00
Sean Hunt
853197557c Replace FIRST_* and LAST_* macros with a generic STMT_RANGE macro
Also rename ABSTRACT to ABSTRACT_STMT

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104018 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 06:22:50 +00:00
Evan Cheng
22c687b642 Added a QQQQ register file to model 4-consecutive Q registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103760 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 02:13:41 +00:00
Evan Cheng
dbf67fefea Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 23:55:47 +00:00
Chandler Carruth
93ca7b60bf Update tablegen to generate shorts instead of chars for subgroup arrays.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103704 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 07:43:47 +00:00
Dan Gohman
a6cb641f48 Add initial kill flag support to FastISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103529 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 23:54:07 +00:00
Douglas Gregor
7d9663c70b Fixes for Microsoft Visual Studio 2010, from Steven Watanabe!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103457 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 06:17:44 +00:00
Sean Callanan
1a8b789a4b Eliminated the classification of control registers into %ecr_
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:59:00 +00:00
Dan Gohman
34dcc6fadc Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:33:48 +00:00
Evan Cheng
b63387afc6 Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103172 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 06:36:08 +00:00
Sean Hunt
44ed2c31a5 Fix some stylistic issues with my last commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103164 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 05:24:38 +00:00
Shantonu Sen
d1dd5ed0ed Add newline to end of file to avoid warning
when building llvm with clang


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103084 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 13:56:46 +00:00
Sean Hunt
dc896a4118 Include the right header for toupper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103073 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 04:31:44 +00:00
Sean Hunt
84e2f959b7 Add an emitter to handle the list of clang statement nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103071 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 04:13:08 +00:00
Chris Lattner
af1465b17b add the ability to associate 'category' names with clang diagnostics
and diagnostic groups.  This allows the compiler to group 
diagnostics together (e.g. "Logic Warning", 
"Format String Warning", etc) like the static analyzer does.  
This is not exposed through anything in the compiler yet.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103050 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 20:44:23 +00:00
Daniel Dunbar
4f83e73a6d MC/Matcher: Add support for over-riding the default MatchInstruction function
name (for example, to allow targets to interpose the actual MatchInstruction
function).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 00:33:13 +00:00
Evan Cheng
b55c8bed9d Add a pseudo instruction REG_SEQUENCE that takes a list of registers and
sub-register indices and outputs a single super register which is formed from
a consecutive sequence of registers.

This is used as register allocation / coalescing aid and it is useful to
represent instructions that output register pairs / quads. For example,
v1024, v1025 = vload <address>
where v1024 and v1025 forms a register pair.

This really should be modelled as
v1024<3>, v1025<4> = vload <address>
but it would violate SSA property before register allocation is done.

Currently we use insert_subreg to form the super register:
v1026 = implicit_def
v1027 - insert_subreg v1026, v1024, 3
v1028 = insert_subreg v1027, v1025, 4
...
      = use v1024
      = use v1028

But this adds pseudo live interval overlap between v1024 and v1025.

We can now modeled it as
v1024, v1025 = vload <address>
v1026 = REG_SEQUENCE v1024, 3, v1025, 4
...
      = use v1024
      = use v1026

After coalescing, it will be
v1026<3>, v1025<4> = vload <address>
...
      = use v1026<3>
      = use v1026


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-01 00:28:44 +00:00
Sean Callanan
a0f914b6c1 Fixes to edis that mark x86 call targets as
memory operands rather than immediate operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102217 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-23 22:17:17 +00:00
Johnny Chen
56a1afb6b0 When doing Thumb disassembly, there's no need to consider t2ADDrSPi12/t2SUBrSPi12,
as their generic counterparts t2ADDri12/t2SUBri12 should suffice.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101929 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 18:45:24 +00:00
Chris Lattner
acfb70f750 stop computing InstImpInputs, it is dead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101881 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 06:30:25 +00:00
Chris Lattner
62bcec82b2 DAGInstruction::ImpOperands is dead after my recent tblgen work, zap it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101880 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 06:28:43 +00:00
Anton Korobeynikov
928eb49cae Make processor FUs unique for given itinerary. This extends the limit of 32
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-18 20:31:01 +00:00
Dan Gohman
b35798347e Fix a bunch of namespace polution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101376 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 17:08:50 +00:00
Benjamin Kramer
be10811323 EDis: Don't include inttypes.h. We support compilers which don't provide it. It was unused anyways.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14 13:56:38 +00:00
Sean Callanan
9899f70a74 Fixed a nasty layering violation in the edis source
code.  It used to #include the enhanced disassembly
information for the targets it supported straight
out of lib/Target/{X86,ARM,...} but now it uses a
new interface provided by MCDisassembler, and (so
far) implemented by X86 and ARM.

Also removed hacky #define-controlled initialization
of targets in edis.  If clients only want edis to
initialize a limited set of targets, they can set
--enable-targets on the configure command line.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101179 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13 21:21:57 +00:00
Johnny Chen
1808e4d251 If all the bit positions are not specified; do not decode the instructions.
We are bound to fail!  For proper disassembly, the well-known encoding bits
of the instruction must be fully specified.

This also removes pseudo instructions from considerations of disassembly,
which is a better design and less fragile than the name matchings.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100899 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09 21:01:02 +00:00
Bob Wilson
ec80e2693a Provide versions of the ARM eh_sjlj_setjmp instructions for non-VFP subtargets
such that the non-VFP versions have no implicit defs of VFP registers.
If any callee-saved VFP registers are marked as having been defined, the
prologue/epilogue code will try to save and restore them.
Radar 7770432.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100892 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09 20:41:18 +00:00
Johnny Chen
e0c74fb1de ARM decoder emitter should print out useful information unconditionally when it
encounters decoding conflicts, instead of wrapping it inside the DEBUG() macro. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100886 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09 19:31:33 +00:00
Johnny Chen
2d16a67b94 Now that Evan Cheng has fixed the coalescer bug (r100804), the workaround code
to avoid memcpy() call is no longer necessary.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100811 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 21:23:54 +00:00
Benjamin Kramer
454c4ce479 Various MSVC warning fixes about truncated 64 bit shifts and const pointers passed to free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100767 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 15:25:57 +00:00
Benjamin Kramer
127dc5e615 Use errs instead of fprintf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 09:42:29 +00:00
Sean Callanan
8f993b8c24 Added support for ARM disassembly to edis.
I also added a rule to the ARM target's Makefile to
build the ARM-specific instruction information table
for the enhanced disassembler.

I will add the test harness for all this stuff in
a separate commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100735 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 00:48:21 +00:00
Chris Lattner
75361b69f3 rename llvm::llvm_report_error -> llvm::report_fatal_error
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100709 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 22:58:41 +00:00
Sean Callanan
5edca81626 Fixed a bug where the disassembler would allow an immediate
argument that had to be between 0 and 7 to have any value,
firing an assert later in the AsmPrinter.  Now, the
disassembler rejects instructions with out-of-range values
for that immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100694 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 21:42:19 +00:00
Eric Christopher
72666f2be9 Fix typo and correct comment somewhat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100691 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 20:58:16 +00:00
Johnny Chen
3c500e6947 Re-enable ARM/Thumb disassembler and add a workaround for a memcpy() call in
ARMDecoderEmitter.cpp, with FIXME comment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100690 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 20:53:12 +00:00
Anton Korobeynikov
96085a36db Initial support for different kinds of FU reservation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100645 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:19:32 +00:00
Jakob Stoklund Olesen
fddb7667ca Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.

This works well because TableGen resolves member references late:

class I : Instruction {
  AddrMode AM = AddrModeNone;
  let TSFlags{3-0} = AM.Value;
}

let AM = AddrMode4 in
def ADD : I;

TSFlags gets the expected bits from AddrMode4 in this example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-05 03:10:20 +00:00
Chris Lattner
35c33bd772 change a ton of code to not implicitly use the "O" raw_ostream
member of AsmPrinter.  Instead, pass it in explicitly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100306 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-04 04:47:45 +00:00
Chandler Carruth
1e86e3fb4b Fix a warning in GCC about a pointless typedef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100268 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-03 04:45:24 +00:00
Chandler Carruth
b421640efa Add the new ARMDecodeEmitter to CMake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100267 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-03 04:36:43 +00:00
Johnny Chen
55f71187a5 Move variable "Bits" declaration/definition into the DEBUG block where its usage
is expected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100247 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 23:13:52 +00:00
Johnny Chen
493a441391 Fixed build warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100244 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 22:51:04 +00:00
Johnny Chen
9981814a40 Change from .../Support/DataTypes.h to .../System/DataTypes.h.
(Fix build failure)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 22:41:06 +00:00
Johnny Chen
b68a3ee82a Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen
backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Reviewed by Chris Latter and Bob Wilson.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 22:27:38 +00:00
Chris Lattner
283d1ceb57 Switch pattern sorting predicate from stable sort -> sort, it
doesn't need to be stable because the patterns are fully ordered.

Add a first level sort predicate that orders patterns in this
order:  1) scalar integer operations 2) scalar floating point 
3) vector int 4) vector float.  This is a trivial sort on their
top level pattern type so it is nice and transitive.  The
benefit of doing this is that simple integer operations are
much more common than insane vector things and isel was trying
to match the big complex vector patterns before the simple
ones because the complexity of the vector operations was much
higher.  Since they can't both match, it is best (for compile
time) to try the simple integer ones first.

This cuts down the # failed match attempts on real code by
quite a bit, for example, this reduces backtracks on crafty
(as a random example) from 228285 -> 188369.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99797 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-29 02:02:45 +00:00
Chris Lattner
4810736134 revert 99795, as mentioned, it is disabled anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99796 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-29 01:58:15 +00:00
Chris Lattner
a0401249e8 Check in a (disabled) failed attempt to improve the ordering of
patterns within the generated matcher.  This works great except
that the sort fails because the relation defined isn't 
transitive.  I have a much simpler solution coming next, but want
to archive the code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99795 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-29 01:56:19 +00:00
Chris Lattner
48e86dbe29 print the complexity of the pattern being matched in the
comment in the generated table.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-29 01:40:38 +00:00
Chris Lattner
2a22cdc716 improve type checking of SDNode operand count. This rejects all cases
where an incorrect number of operands is provided to an sdnode instead
of just a few cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 08:48:47 +00:00
Chris Lattner
caa8870fe0 finally remove the immAllOnesV_bc/immAllZerosV_bc patterns
and those derived from them.  These are obnoxious because
they were written as: PatLeaf<(bitconvert).  Not having an
argument was foiling adding better type checking for operand
count matching up with what was required (in this case,
bitconvert always requires an operand!)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99759 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 08:43:23 +00:00
Chris Lattner
7a0eb91b4c teach tblgen to allow patterns like (add (i32 (bitconvert (i32 GPR))), 4),
transforming it into (add (i32 GPR), 4).  This allows us to write type
generic multi patterns and have tblgen automatically drop the bitconvert
in the case when the types align.  This allows us to fold an extra load
in the changed testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99756 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 08:38:32 +00:00
Chris Lattner
b775b1e20b validate that input sdnodes don't exist in an output pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 06:57:56 +00:00
Chris Lattner
c217305f76 eliminate a bunch of code duplication in ParseTreePattern
by rotating it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 06:50:34 +00:00
Chris Lattner
c812261221 SDTCisVT<0, isVoid> is not valid, reject it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99744 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 06:04:39 +00:00
Chris Lattner
aa4e3391c8 add an optimized form of OPC_EmitMergeInputChains for the 1, 0 and
1, 1 cases which are by-far the most frequent.  This shrinks the X86
isel table from 77014 -> 74657 bytes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99740 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 05:50:16 +00:00
Chris Lattner
b4a52b04bd fix a long standing fixme, which required fixing a bunch of other
issues to get here.  We now trim the result type list of the
CompleteMatch or MorphNodeTo operation to be the same size as the
thing we're matching.  this means that if you match (add GPR, GPR)
with an instruction that produces a normal result and a flag that
we now trim the result in tblgen instead of having to do it 
dynamically.  This exposed a bunch of inconsistencies in result
counting that happened to be getting lucky since the days of the
old isel.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99728 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 20:45:15 +00:00
Chris Lattner
0d7952ed5a fix CodeGenTarget::getRegisterVTs to not return the
same vt multiple times for a register.  For example,
ECX is in 5 different i32 reg classes, just return 
1 i32 instead of 5.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99727 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 20:32:26 +00:00
Chris Lattner
9414ae5291 hoist some funky logic into CodeGenInstruction
from two places in CodeGenDAGPatterns.cpp, and
use it in DAGISelMatcherGen.cpp instead of using
an incorrect predicate that happened to get lucky
on our current targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99726 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 20:09:24 +00:00
Chris Lattner
0be6fe7139 continue pushing tblgen's support for nodes with multiple
results forward.  We can now handle an instruction that 
produces one implicit def and one result instead of one or
the other when not at the root of the pattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99725 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 19:15:02 +00:00
Chris Lattner
5d3569e93c fix a bug in my recent patch that increased opcode size to 2 bytes:
the index comments nested under OPC_SwitchOpcode were off by one.
This fixes the comments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99722 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 18:49:33 +00:00
Dan Gohman
f65f294c99 Remove an unnecessary #include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99714 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 16:33:36 +00:00
Chris Lattner
310adf1c6f remove parallel support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99703 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 02:53:27 +00:00
Jakob Stoklund Olesen
70feca409e Teach TableGen to understand X.Y notation in the TSFlagsFields strings.
Remove much horribleness from X86InstrFormats as a result. Similar
simplifications are probably possible for other targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99539 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 18:52:01 +00:00
Chris Lattner
d5d5a3dcba Change tblgen to emit FOOISD opcode names as two
bytes instead of one byte.  This is important because
we're running up to too many opcodes to fit in a byte
and it is aggrevated by FIRST_TARGET_MEMORY_OPCODE
making the numbering sparse.  This just bites the
bullet and bloats out the table.  In practice, this
increases the size of the x86 isel table from 74.5K
to 76K.  I think we'll cope :)

This fixes rdar://7791648


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99494 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 06:33:05 +00:00
Jakob Stoklund Olesen
d1baa252c4 Fix evil TableGen bug in template parameters with defaults.
If a TableGen class has an initializer expression containing an X.Y subexpression,
AND X depends on template parameters,
AND those template parameters have defaults,
AND some parameters with defaults are beyond position 1,
THEN parts of the initializer expression are evaluated prematurely with the default values when the first explicit template parameter is substituted, before the remaining explicit template parameters have been substituted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99492 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 06:23:34 +00:00
Chris Lattner
084df627c8 add plumbing for handling multiple result nodes
in some more places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99366 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:41:19 +00:00
Chris Lattner
cc87830732 implement SDTCisVTSmallerThanOp with EnforceSmallerThan
instead of reimplementing it wrong and poorly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99357 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:06:46 +00:00
Chris Lattner
66fb9d26c6 bring sanity to EnforceVectorEltType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:01:16 +00:00
Chris Lattner
640a3f5309 Cleanup getImplicitType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99353 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 23:50:31 +00:00
Chris Lattner
9972aff7da reject void in intrinsic type lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99347 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 23:46:27 +00:00
Chris Lattner
93dc92e412 Change intrinsic result type for void to store it as an empty list
instead of as a single element list with VoidTy.  Now with a fix
for the verifier.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-22 20:56:36 +00:00
Daniel Dunbar
32f6a8b8bb Fix suggested parentheses warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99111 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-21 01:38:21 +00:00
Eric Christopher
d7de54068c Revert r99009 temporarily it seems to be breaking the bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99011 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 23:04:23 +00:00
Chris Lattner
26e763753b Change intrinsic result type for void to store it as an empty list
instead of as a single element list with VoidTy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99009 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 22:40:56 +00:00
Chris Lattner
2e68a02c26 make getOperandNum a static function (since it's just used by
ApplyTypeConstraint) and make it handle multiple result nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99003 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 21:56:21 +00:00
Chris Lattner
d734919465 major surgery on tblgen: generalize TreePatternNode
to maintain a list of types (one for each result of
the node) instead of a single type.  There are liberal
hacks added to emulate the old behavior in various
situations, but they can start disolving now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98999 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 21:37:09 +00:00
Chris Lattner
774ce29399 make FillWithPossibleTypes take a predicate to filter types so that
we don't blow the smallvector as often.  No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98968 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 17:41:26 +00:00
Chris Lattner
1e50631675 resolve fixme: we now infer the instruction-level 'isvariadic' bit
from the pattern if present, and we use it instead of the bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98938 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 05:34:15 +00:00
Chris Lattner
e8cabf3c2e add a new SDNPVariadic SDNP node flag, and use it in
dag isel gen instead of instruction properties.  This
allows the oh-so-useful behavior of matching a variadic
non-root node.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98934 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 05:07:09 +00:00
Chris Lattner
5a9b8fb95c rewrite EnforceSmallerThan to be less bone headed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98933 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 04:54:36 +00:00
Daniel Dunbar
65f35d5703 Fix -Asserts warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98927 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 03:18:20 +00:00
Chris Lattner
aac5b5b2e5 eliminate the last use of EEVT::isUnknown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98918 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 01:14:27 +00:00
Chris Lattner
e14d2e210d Finally change the instruction looking map to be a densemap from
record* -> instrinfo instead of std::string -> instrinfo.

This speeds up tblgen on cellcpu from 7.28 -> 5.98s with a debug
build (20%).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98916 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 01:07:44 +00:00
Chris Lattner
6a91b18e57 make inst_begin/inst_end iterate over InstructionsByEnumValue.
Use CodeGenTarget::getInstNamespace in one place and fix it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 01:00:55 +00:00
Chris Lattner
01dcecc214 revert 98912
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98914 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:50:47 +00:00
Chris Lattner
a28bc686fa make inst_begin/inst_end iterate over InstructionsByEnumValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98912 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:40:22 +00:00
Chris Lattner
f65027842e change Target.getInstructionsByEnumValue to return a reference
to a vector that CGT stores instead of synthesizing it on every 
call.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98910 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:34:35 +00:00
Chris Lattner
e4e8bb1541 factor copy and paste code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98908 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:23:20 +00:00
Chris Lattner
b61e09de6d don't go through getInstructions().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98906 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:18:23 +00:00
Chris Lattner
f30187a363 look up instructions by record, not by name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:07:20 +00:00
Chris Lattner
928795387f expand tblgen's support for instructions with implicit defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98900 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 23:57:40 +00:00
Chris Lattner
6c6ba36493 infer results of a pattern from implicit defs. This allows you to do something
like this:

 def : Pat<(add ...),
           (FOOINST)>;

When fooinst only has a single implicit def (e.g. to R1).  This will be handled
as if written as (set R1, (FOOINST ...))



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 23:15:10 +00:00
Chris Lattner
f506b6b471 capture implicit uses and defs in CodeGenInstruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 21:42:03 +00:00
Chris Lattner
ef988984d7 simplify this code, the # of sets in the pattern for an instruction
shouldn't change this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98872 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 21:15:05 +00:00
Chris Lattner
0b6c926856 disallow concatenation of two dags with different operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98871 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 21:07:51 +00:00
Chris Lattner
f55eed299b rewrite this to not artificially force concat the ins/outs list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98870 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 21:07:39 +00:00
Chris Lattner
b0be4d261b eliminate support for "ops" in the input/output list of an
instruction.  Instructions must use 'ins' and 'outs' now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98868 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 20:56:35 +00:00
Chris Lattner
cedef1ccf0 remove some code that was working around old sparc v9 backend bugs.
Add checking that the input/output operand list in spelled right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98865 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 20:50:52 +00:00
Daniel Dunbar
8cc9c0c487 MC/AsmMatcher: Add support for target specific "instruction cleanup" functions,
to allow custom post-processing of matched instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98857 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 20:05:56 +00:00
Kovarththanan Rajaratnam
e7e891f6af Add an extra newline to separate PP directives from the contents
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 13:16:38 +00:00
Bob Wilson
49d9dc4dd2 --- Reverse-merging r98637 into '.':
U    test/CodeGen/ARM/tls2.ll
U    test/CodeGen/ARM/arm-negative-stride.ll
U    test/CodeGen/ARM/2009-10-30.ll
U    test/CodeGen/ARM/globals.ll
U    test/CodeGen/ARM/str_pre-2.ll
U    test/CodeGen/ARM/ldrd.ll
U    test/CodeGen/ARM/2009-10-27-double-align.ll
U    test/CodeGen/Thumb2/thumb2-strb.ll
U    test/CodeGen/Thumb2/ldr-str-imm12.ll
U    test/CodeGen/Thumb2/thumb2-strh.ll
U    test/CodeGen/Thumb2/thumb2-ldr.ll
U    test/CodeGen/Thumb2/thumb2-str_pre.ll
U    test/CodeGen/Thumb2/thumb2-str.ll
U    test/CodeGen/Thumb2/thumb2-ldrh.ll
U    utils/TableGen/TableGen.cpp
U    utils/TableGen/DisassemblerEmitter.cpp
D    utils/TableGen/RISCDisassemblerEmitter.h
D    utils/TableGen/RISCDisassemblerEmitter.cpp
U    Makefile.rules
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/Makefile
U    lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
U    lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U    lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
D    lib/Target/ARM/Disassembler
U    lib/Target/ARM/ARMInstrFormats.td
U    lib/Target/ARM/ARMAddressingModes.h
U    lib/Target/ARM/Thumb2ITBlockPass.cpp


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16 16:59:47 +00:00
Johnny Chen
d30a98e43a Initial ARM/Thumb disassembler check-in. It consists of a tablgen backend
(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.

We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>.  See, for example, A8.6.57/58/60.

And modified test cases to not expect '+' in +reg or #+num.  For example,

; CHECK:       ldr.w	r9, [r7, ]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98637 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16 16:36:54 +00:00
Chris Lattner
5f19c43161 don't form a RecordChild or CheckChildType for child #'s over 7, we don't
have enums for them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98597 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16 00:35:11 +00:00
Chris Lattner
e002da34ef eliminate some #if 0 code I added in r96905, type inference
now enforces that input/output named values have hte same type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98535 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-15 06:03:22 +00:00
Chris Lattner
2cacec55f9 Completely rewrite tblgen's type inference mechanism,
changing the primary datastructure from being a 
"std::vector<unsigned char>" to being a new TypeSet class
that actually has (gasp) invariants!

This changes more things than I remember, but one major
innovation here is that it enforces that named input 
values agree in type with their output values.

This also eliminates code that transparently assumes (in 
some cases) that SDNodeXForm input/output types are the
same, because this is wrong in many case.

This also eliminates a bug which caused a lot of ambiguous
patterns to go undetected, where a register class would
sometimes pick the first possible type, causing an
ambiguous pattern to get arbitrary results.

With all the recent target changes, this causes no 
functionality change!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98534 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-15 06:00:16 +00:00
Evan Cheng
5e81716425 Check in tablegen changes to fix disassembler related failures caused by r98465.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98468 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 05:15:39 +00:00
Chris Lattner
43e4754817 Node arguments to type casts can have names too. This code
needs to be majorly refactored, but this spot bugfix allows
things like:

 def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
                             (vector_shuffle (v4i32 node:$lhs), node:$rhs), [{
...



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97952 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-08 18:36:19 +00:00
Chris Lattner
81d6d52592 turn off debug spew
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97912 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-07 07:21:24 +00:00
Chris Lattner
6fd326b7ff more factoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97911 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-07 07:20:49 +00:00
Chris Lattner
9cdd9659c3 teach tblgen to be more aggressive when factoring CheckType nodes.
Now it will factor things like this:

CheckType i32
  ...
CheckOpcode ISD::AND
  CheckType i64
  ...

into:

SwitchType:
  i32: ...
  i64:
    CheckOpcode ISD::AND
    ...

This shrinks hte table by a few bytes, nothing spectacular.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97908 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-07 07:01:28 +00:00
Chris Lattner
48aa5756a2 add some helper functions and implement isContradictory
for CheckValueTypeMatcher.  The isContradictory implementation
helps us factor better, shrinking x86 table from 79144 -> 78896
bytes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97905 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-07 06:29:26 +00:00
Mikhail Glushenkov
b5c4239606 Make it not an error to specify -O* options several times.
As in 'llvmc -O2 -O2 test.c'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97787 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-05 04:46:39 +00:00
Chris Lattner
57fcd03611 so hey, it turns out that the histogram was completely wrong, because
we sometimes emit nodes multiple times to string buffers to size them.
Compute the histogram correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97708 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-04 01:34:29 +00:00
Chris Lattner
6b4ae71725 zap fixme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97705 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-04 01:26:00 +00:00
Chris Lattner
9752fb10a4 now that complexpatterns are all emitted at the end of the match
sequence, just emit instruction predicates right before them.  This
exposes yet more factoring opportunitites, shrinking the X86 table 
to 79144 bytes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97704 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-04 01:25:36 +00:00
Chris Lattner
57bf8a483e change the new isel matcher to emit ComplexPattern matches
as the very last thing before node emission.  This should
dramatically reduce the number of times we do 'MatchAddress'
on X86, speeding up compile time.  This also improves comments
in the tables and shrinks the table a bit, now down to 
80506 bytes for x86.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97703 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-04 01:23:08 +00:00
Chris Lattner
d1aca7c8b4 enhance comment output to specify what recorded slot
numbers a ComplexPat will match into.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97696 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-04 00:28:05 +00:00
Chris Lattner
cfe2eab744 introduce a new SwitchTypeMatcher node (which is analogous to
SwitchOpcodeMatcher) and have DAGISelMatcherOpt form it.  This
speeds up selection, particularly for X86 which has lots of 
variants of instructions with only type differences.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97645 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03 06:28:15 +00:00
Chris Lattner
d272fee398 the sorting predicate should work for comparing an element
to itself, even though this isn't wildly useful.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97574 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 18:15:02 +00:00
Chris Lattner
4a3ac62332 eliminate CodeGen/DAGISelHeader.h, it is empty now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97556 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 06:36:28 +00:00
Chris Lattner
c6d7ad3c7d Rewrite chain handling validation and input TokenFactor handling
stuff now that we don't care about emulating the old broken 
behavior of the old isel.  This eliminates the 
'CheckChainCompatible' check (along with IsChainCompatible) which
did an incorrect and inefficient scan *up* the chain nodes which
happened as the pattern was being formed and does the validation
at the end in HandleMergeInputChains when it forms a structural 
pattern.  This scans "down" the graph, which means that it is
quickly bounded by nodes already selected.  This also handles
token factors that get "trapped" in the dag.

Removing the CheckChainCompatible nodes also shrinks the 
generated tables by about 6K for X86 (down to 83K).

There are two pieces remaining before I can nuke PreprocessRMW:
1. I xfailed a test because we're now producing worse code in a 
   case that has nothing to do with the change: it turns out that
   our use of MorphNodeTo will leave dead nodes in the graph
   which (depending on how the graph is walked) end up causing
   bogus uses of chains and blocking matches.  This is really 
   bad for other reasons, so I'll fix this in a follow-up patch.

2. CheckFoldableChainNode needs to be improved to handle the TF.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97539 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 02:22:10 +00:00
Chris Lattner
38fd96731c add some missing \n's
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97527 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 00:13:03 +00:00
Chris Lattner
8b30b8dd33 fixme resolved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97517 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01 23:08:51 +00:00
Chris Lattner
e60f7b4412 remove a little hack I did for the old isel, not needed
now that it is gone.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97516 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01 22:51:11 +00:00
Chris Lattner
67ea6a7111 resolve some fixmes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97515 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01 22:49:06 +00:00
Chris Lattner
01bcd947bf resolve a fixme and simplify code by moving insertion of the
EmitMergeInputChainsMatcher node up into EmitResultCode.  This
doesn't have much of an effect on the generated code, the X86
table is exactly the same size.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97514 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01 22:46:42 +00:00
Chris Lattner
405f1252b9 resolve a fixme by having the .td file parser reject thigns like
(set GPR, somecomplexpattern)

if somecomplexpattern doesn't declare what it can match.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01 22:29:19 +00:00
Chris Lattner
7c720fc33a remove dead code, simplify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97510 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01 22:19:47 +00:00
Chris Lattner
117ccb7e51 Fix PR2590 by making PatternSortingPredicate actually be
ordered correctly.  Previously it would get in trouble when
two patterns were too similar and give them nondet ordering.
We force this by using the record ID order as a fallback.

The testsuite diff is due to alpha patterns being ordered
slightly differently, the change is a semantic noop afaict:

< 	lda $0,-100($16)
---
> 	subq $16,100,$0



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97509 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01 22:09:11 +00:00
Chris Lattner
f94bc54757 tolerate factoring the *last* node for CellSPU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97508 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01 22:04:33 +00:00
Chris Lattner
adc5347b54 optimize tblgen compile time by eliminating the old isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97504 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01 21:49:54 +00:00
Chris Lattner
459eeedbe0 don't emit the old sdnodexform stuff for the new isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97486 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01 19:39:15 +00:00
Chris Lattner
8a01c8d00d Turn on the new isel by default. Here are some fun numbers
with a release-asserts build on x86-64-darwin10:

LLC Size:
Old: 15,426,852
New: 12,759,140  (down 2.7M)

LLI Size:
Old: 9,926,876
New: 8,864,292   (down 1.1M)

X86ISelDAGToDAG.o size:
Old: 1,401,232
New:   162,868   (down 1.3M)

Time to build X86ISelDAGToDAG.o:
Old: 67.147u 2.060s 1:09.78
New:  4.234u 0.387s 0:04.77



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97475 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01 19:05:25 +00:00
Torok Edwin
5520ad4dd9 Missed a \n in previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97472 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01 19:00:55 +00:00
Torok Edwin
5c7fc88b55 Add command-line flag to tblgen to turn off generating comments for the new
isel (defaults it to generate comments).
This reduces the size of the generated source file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97470 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01 18:49:10 +00:00
Chris Lattner
60c0e37afc Emit type checks late instead of early, this encourages
structural matching code to be factored and shared this
shrinks the X86 isel table from 86537 to 83890 bytes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97442 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01 07:54:59 +00:00
Chris Lattner
bd8965a7d9 Emit a redundant check for immediates at root context, e.g. (imm 0).
This allows formation of OpcodeSwitch for top level patterns, in
particular on X86.  This saves about 1K of data space in the x86
table and makes the dispatch much more efficient.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97440 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01 07:27:07 +00:00
Chris Lattner
fa342faef9 eliminate the CheckMultiOpcodeMatcher code and have each
ComplexPattern at the root be generated multiple times, once
for each opcode they are part of.  This encourages factoring
because the opcode checks get treated just like everything
else in the matcher.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97439 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01 07:17:40 +00:00
Chris Lattner
eb66921adb add a new OPC_SwitchOpcode which is semantically equivalent
to a scope where every child starts with a CheckOpcode, but
executes more efficiently.  Enhance DAGISelMatcherOpt to 
form it.

This also fixes a bug in CheckOpcode: apparently the SDNodeInfo
objects are not pointer comparable, we have to compare the
enum name.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97438 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01 06:59:22 +00:00
Chris Lattner
c99b5a25bb pull MarkFlagResult out from between an EmitNode/CompleteMatch
pair.  This encourages MorphNodeTo formation, this gets us 200
more MorphNodeTo's on X86 and shrinks the table a bit.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01 02:33:14 +00:00
Chris Lattner
0cebe6181a enhance RecordNode and RecordChild comments to indicate what
slot they're recording into, no functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97433 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01 02:24:17 +00:00
Chris Lattner
e9eeda878b Emit redundant opcode checks for andimm and orimm tests at root
so that we get grouping at the top level.

Add an optimization to reorder type check & record nodes
after opcode checks.  We prefer to expose tree shape 
matching which improves grouping and will enhance the next
optimization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97432 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-01 02:15:34 +00:00