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4b181c87de
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16243 Commits

Author SHA1 Message Date
Chris Lattner
4b181c87de Convert 'and' to single instance of a multipattern 
which instantiates the 34 versions of and all in one
swoop.  The BaseOpc/BaseOpc2/BaseOpc4 stuff should not
be required, but tblgen's feeble brain explodes when I
use Or4<BaseOpc>.V in the multipattern.

No change in the generated .inc files.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115893 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 01:10:20 +00:00
Jim Grosbach
a4257162be Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115890 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:53:56 +00:00
Chris Lattner
511c686f76 add a new BinOpAI class to represent the immediate form that directly acts on EAX. 
This does change the generated .inc files to include the implicit use/def of eax.
Since these instructions are only generated by the assembler and disassembler it
doesn't actually matter though.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115885 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:43:39 +00:00
Jim Grosbach
3bbdcea49a Allow use of the 16-bit literal move instruction in CMOVs for ARM mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115884 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:42:42 +00:00
Chris Lattner
1bb9adae4c add a bunch of classes for other common patterns. 
As usual, no change in generated .inc files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115882 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:35:28 +00:00
Chris Lattner
2b8d30d080 Define a new BinOpRI8 class and use it to define the imm8 versions of and. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115880 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:12:45 +00:00
Jakob Stoklund Olesen
635127a8c6 Constrain the offset register to a *_NOSP register class when inserting LEA 
instructions.

This unbreaks the machine code verifier and fixes PR8317.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115879 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:07:26 +00:00
Chris Lattner
78266110bf add the pattern operator to match to X86TypeInfo, use this to 
convert AND64ri32 to use BinOpRI.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115878 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 00:01:39 +00:00
Jakob Stoklund Olesen
8f42a19fb0 Properly handle GR32_NOSP in X86RegisterInfo::getMatchingSuperRegClass. 
This function looks like it is about ready to be generated by TebleGen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115876 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 23:56:46 +00:00
Jim Grosbach
fa7fb64fad remove trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115860 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 22:46:47 +00:00
Jason W Kim
def9ac48b7 First in a sequence of ARM/MC/*ELF* specific work. 
Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115859 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 22:36:46 +00:00
Jim Grosbach
3c38f96af2 Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115853 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 22:01:26 +00:00
Jim Grosbach
1d6111c5ac Kill of the vestiges of the 'call' Modifier (no longer needed for PLT). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115845 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 21:36:43 +00:00
Jim Grosbach
35636281c7 Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-needed 
"lane" operand modifier.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115843 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 21:22:32 +00:00
Jim Grosbach
65dc30340c Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually be 
pseudo instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115840 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 21:16:16 +00:00
Jim Grosbach
7cd2729d2a Add a 'pattern' arg to the ARM PseudoNeonI class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115831 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 20:36:55 +00:00
Jim Grosbach
4dea941c8d target operand flag values aren't a bitmask 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115798 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 16:51:55 +00:00
Evan Cheng
a0792de66c - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This 
allow target to correctly compute latency for cases where static scheduling
  itineraries isn't sufficient. e.g. variable_ops instructions such as
  ARM::ldm.
  This also allows target without scheduling itineraries to compute operand
  latencies. e.g. X86 can return (approximated) latencies for high latency
  instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
  e.g. ldm and those used by store multiple instructions, e.g. stm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 06:27:31 +00:00
Chris Lattner
b2fc409827 enhance X86TypeInfo to include information about the encoding and 
operand kind for immediates.  Use these to define a new BinOpRI
class and switch AND8/16/32ri over to it.  AND64ri32 needs some
more refactoring before it can make the switcheroo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115752 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 05:55:42 +00:00
Chris Lattner
3ab0b59aad add a class for _REV nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115748 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 05:35:22 +00:00
Chris Lattner
08808f9733 sink more intelligence into the ITy base class. Now it knows 
that i8 operations are even and i16,i32,i64 operations have a
low opcode bit set (they are odd).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115747 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 05:28:38 +00:00
Chris Lattner
44402c0701 refactor things a bit, now the REX_W and OpSize prefix bytes are inferred from the type info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115745 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 05:20:57 +00:00
Chris Lattner
da4b361726 with tblgen suitably extended, we can now get the load node from typeinfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115744 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 04:58:43 +00:00
Chris Lattner
417b54354b lets go all meta and define new X86 type wrappers that declare the associated 
gunk that goes along with an MVT (e.g. reg class, preferred load operation,
memory operand)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115727 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 00:45:24 +00:00
Chris Lattner
ff27af206e introduce a new BinOpRM class and use it to factor AND*rm. This points out 
that I need a heavier handed approach to get ultimate factorization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115726 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 00:30:49 +00:00
Chris Lattner
c7252ce743 remove the !nameconcat tblgen feature. It "shorthand" and only used in 4 places 
where !cast is just as short.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115722 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 00:19:21 +00:00
Chris Lattner
78caacc226 replace stuff like: 
let AsmString = !strconcat(
                     !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
                     !strconcat("\t", asm));

with:

  let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);

:)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115720 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 00:05:18 +00:00
Chris Lattner
8d978a75b4 allow !strconcat to take more than two operands to eliminate 
!strconcat(!strconcat(!strconcat(!strconcat

Simplify some x86 td files to use it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115719 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 23:58:18 +00:00
Eric Christopher
e540a6f94a Comment out fastisel debugging message. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115717 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 23:50:58 +00:00
Chris Lattner
20b2499a7c associate the instruction suffix letter with the integer gpr 
register class, and use this to simplify use of BinOpRR.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115716 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 23:43:04 +00:00
Chris Lattner
e00047c906 introduce a new BinOpRR class, and convert 4 and instructions to use it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115715 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 23:32:05 +00:00
Eric Christopher
022b7fb045 Random cleanup and make the intermediate register in fptosi a 
32-bit fp reg, not 64-bit.

Fixes SingleSource.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115711 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 23:13:24 +00:00
Chris Lattner
6dbbff9172 Move cmov pseudo instructions to InstrCompiler, 
convert all the rest of the cmovs to the multiclass,
with good results:

 X86InstrCMovSetCC.td |  598 +--------------------------------------------------
 X86InstrCompiler.td  |   61 +++++
 2 files changed, 77 insertions(+), 582 deletions(-)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115707 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 23:09:10 +00:00
Chris Lattner
25cbf504fe Use #NAME# to have the CMOV multiclass define things with the same names as before 
(e.g. CMOVBE16rr instead of CMOVBErr16).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115705 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 23:00:14 +00:00
Chris Lattner
df72eaef3d enhance tblgen to support anonymous defm's, use this to 
simplify the X86 CMOVmr's.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115702 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 22:51:56 +00:00
Chris Lattner
286997c745 convert cmov mr patterns to use a multipattern. Death to redundancy 
and verbosity


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115701 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 22:42:54 +00:00
Chris Lattner
d350e4757e switch CMOVBE to the multipattern: 
21 insertions(+), 53 deletions(-)

Moar change coming before I switch the rest.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115697 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 22:23:58 +00:00
Chris Lattner
e583c892d8 fix a bug I introduced in r115669, which ended up with MOV64mr_TC 
not getting marked as mayStore.  This fixes llvm-gcc bootstrap.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115693 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 22:16:48 +00:00
Chris Lattner
b484213d1b add a multiclass for cmov's, but don't start using it yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115692 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 22:01:02 +00:00
Chris Lattner
d244699067 use a multipattern to define setcc instructions: 
X86InstrCMovSetCC.td |  200 ++++++---------------------------------------------
 1 file changed, 27 insertions(+), 173 deletions(-)




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115689 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 21:34:29 +00:00
Chris Lattner
2c383d8c4d move SETB pseudos into the same place in InstrCompiler.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115686 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 21:18:04 +00:00
Chris Lattner
508fc4708b Replace a gross hack (the MOV64ri_alt instruction) with a slightly less 
gross hack (having the asmmatcher handle the alias).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115685 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 21:09:45 +00:00
Chris Lattner
748a2fe917 distribute the rest of the contents of X86Instr64bit.td out to 
the right places.  X86Instr64bit.td now dies, long live x86-64!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115669 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 20:49:15 +00:00
Chris Lattner
10701928ff move the rest of the simple 64-bit arithmetic into InstrArithmetic.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115663 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 20:35:37 +00:00
Chris Lattner
5bbbcdb1d8 continue moving 64-bit stuff into X86InstrArithmetic.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115660 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 20:23:31 +00:00
Jim Grosbach
d86609fca4 Increase the number of bits used internally by the ARM target to represent the 
addressing mode from four to five.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115645 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 18:14:55 +00:00
Chris Lattner
64227940e7 move 64-bit add and adc to InstrArithmetic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115632 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 16:59:08 +00:00
Chris Lattner
c7d4655b57 rewrote two addr constraints so that they are only set, not set and then nestedly cleared. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115631 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 16:52:25 +00:00
Chris Lattner
6367cfc470 split the 32-bit integer arithmetic instructions out to their own file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115627 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 16:39:12 +00:00
Chris Lattner
5249ff34fb integrate the 64-bit shifts into X86InstrShiftRotate.td. Enough for tonight. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115608 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-05 07:13:35 +00:00