Commit Graph

2774 Commits

Author SHA1 Message Date
Evan Cheng
4f6b4674be Teach bottom up pre-ra scheduler to track register pressure. Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 06:09:07 +00:00
Chris Lattner
4dbbe3433f prune #includes a little.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108929 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 21:17:29 +00:00
Jim Grosbach
f084a5e81d Using BIC for immediates needs an extra bump for its complexity to get
instruction selection to prefer it when possible. rdar://7903972

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108844 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 16:07:04 +00:00
Jim Grosbach
26ede6834e Removed un-used code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108841 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 14:51:32 +00:00
Eric Christopher
72852a8cfb Constify some arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108812 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 06:52:21 +00:00
Daniel Dunbar
7b81a0ef17 Update CMake files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108787 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 00:08:13 +00:00
Chris Lattner
f447a5f144 sink the arm implementations of ASmPrinter and MCInstLower
out of the AsmPrinter directory into libarm.  Now the
ARM InstPrinters depend jsut on the MC stuff, not on vmcore
or codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108783 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 23:44:46 +00:00
Evan Cheng
d70f57b254 ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 22:15:08 +00:00
Jim Grosbach
e1102caf86 Since ARM emits inline jump tables as part of the ConstantIsland pass,
it should set the jump table encloding the EK_Inline. This prevents
a second, unused, copy of the table from being emitted after the function
body. PR6581.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108730 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 17:20:38 +00:00
Jim Grosbach
350afb16ec revert so I can get the right PR# in the log message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108727 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 17:19:40 +00:00
Jim Grosbach
0bb9895a78 Since ARM emits inline jump tables as part of the ConstantIsland pass,
it should set the jump table encloding the EK_Inline. This prevents
a second, unused, copy of the table from being emitted after the function
body. PR7499.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108722 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 17:18:28 +00:00
Daniel Dunbar
d73ada7d24 Target: Give the TargetAsmParser access to the TargetMachine.
- Unfortunate, but necessary for now to handle subtarget instruction matching. Eventually we should factor out the lower level target machine information so we don't need to do this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108664 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 00:33:49 +00:00
Jim Grosbach
5423856e44 Add combiner patterns to more effectively utilize the BFI (bitfield insert)
instruction for non-constant operands. This includes the case referenced
in the README.txt regarding a bitfield copy.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108608 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-17 03:30:54 +00:00
Jim Grosbach
dd7d28a17b add BFI to getTargetNodeName()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108603 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-17 01:50:57 +00:00
Jim Grosbach
15a2f2eff8 Fix logic think-o
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108601 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-17 01:22:19 +00:00
Eric Christopher
697cba8ec2 Remove unnecessary check that was subsumed into canRealignStack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108588 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-17 00:33:04 +00:00
Eric Christopher
d4c36cec1d Make more explicit and add some currently disabled error messages for
stack realignment on ARM.

Also check for function attributes as we do on X86 as well as
make explicit that we're checking can as well as needs in this function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108582 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-17 00:27:24 +00:00
Jim Grosbach
469bbdb597 Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction
and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 23:05:05 +00:00
Jakob Stoklund Olesen
78e6e00922 Remove the isMoveInstr() hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 22:35:46 +00:00
Jakob Stoklund Olesen
c66756ba16 Use a small local function for a single remaining late isMoveInstr call in
Thumb2ITBlockPass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108564 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 22:35:32 +00:00
Bill Wendling
7431beaba2 Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and
thus is a much more meaningful name.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 22:20:36 +00:00
Evan Cheng
60108e96bb Split -enable-finite-only-fp-math to two options:
-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108465 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-15 22:07:12 +00:00
Eli Friedman
4baa8ebc93 Random note about bswap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108396 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-15 02:20:38 +00:00
Bob Wilson
273ff31e13 Remove restriction on NEON alignment values. Some of the NEON ld/st
instructions use different values (e.g., 2-byte or 4-byte alignment).
Also fix ARMInstPrinter to print these alignments as bits instead of bytes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108386 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 23:54:43 +00:00
Benjamin Kramer
38e59891ee Don't pass StringRef by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108366 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 22:38:02 +00:00
Jim Grosbach
502e0aa628 Improve 64-subtraction of immediates when parts of the immediate can fit
in the literal field of an instruction. E.g.,
long long foo(long long a) {
  return a - 734439407618LL;
}

rdar://7038284



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108339 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 17:45:16 +00:00
Bob Wilson
fed76ffa56 Add missing address register update to t2LDM_RET instruction.
Patch by Brian Lucas. PR7636.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108332 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 16:02:13 +00:00
Eli Friedman
54cc0e12da A couple potential optimizations inspired by comment 4 in PR6773.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108328 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 06:58:26 +00:00
Bob Wilson
7e3f0d2690 Add support for NEON VMVN immediate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108324 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 06:31:50 +00:00
Bob Wilson
046afdb50b The bits in the cmode field of 32-bit VMOV immediate instructions all depend
of the value of the immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108323 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 06:30:44 +00:00
Bob Wilson
9e82bf12a0 Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes.
Radar 7373643.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108303 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 01:22:12 +00:00
Bob Wilson
cba270d042 Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent
NEON VMOV-immediate instructions.  This simplifies some things.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108275 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 21:16:48 +00:00
Evan Cheng
218977b53e Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108258 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 19:27:42 +00:00
Evan Cheng
7a41599962 Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108256 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 19:21:50 +00:00
Bob Wilson
6dce00ced4 Move NEON "modified immediate" encode/decode into ARMAddressingModes.h to
avoid replicated code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108227 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 04:44:34 +00:00
Bob Wilson
c7a797b82b Remove some code that doesn't appear to do anything. All the ARM call
instructions already have implicit defs of LR.  The comment suggests that
this is intended to fix something like pr6111, but it doesn't really do
that either.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108186 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 20:22:45 +00:00
Duncan Sands
3472766f9e Convert some tab stops into spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108130 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12 08:16:59 +00:00
Jakob Stoklund Olesen
600f171486 RISC architectures get their memory operand folding for free.
The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108099 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 19:19:13 +00:00
Rafael Espindola
d6d7abaf4e Make getPhysicalRegisterRegClass non-virtual. Should be able to remove it soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 16:49:10 +00:00
Jakob Stoklund Olesen
ac27366700 Replace copyRegToReg with copyPhysReg for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108078 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 06:33:54 +00:00
Rafael Espindola
cbeeae23c3 Fix va_arg for doubles. With this patch VAARG nodes always contain the
correct alignment information, which simplifies ExpandRes_VAARG a bit.

The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:

* The 's' in target data: If this is set to the minimal alignment of any
  argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
  example.
* The getTransientStackAlignment method. It is possible for an architecture to
  have argument less aligned than what we maintain the stack pointer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108072 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 04:01:49 +00:00
Chandler Carruth
68eec39bca Add parentheses yet again to satisfy GCC's warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108043 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10 12:06:22 +00:00
Jakob Stoklund Olesen
1f32340d95 Automatically fold COPY instructions into stack load/store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108012 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 20:43:13 +00:00
Jim Grosbach
6c7d3a16b3 In the presence of variable sized objects, allocate an emergency spill slot.
rdar://8131327

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108008 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 20:27:06 +00:00
Bob Wilson
a0148c360e Print "dregpair" NEON operands with a space between them, for readability and
consistency with other instructions that have lists of register operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107944 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:47:20 +00:00
Evan Cheng
5d115a0ff9 Check for FiniteOnlyFPMath as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 20:12:24 +00:00
Bob Wilson
1425c6a927 The NEONPreAllocPass should never have to assign fixed registers anymore.
This pass can go away entirely soon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107892 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 17:45:26 +00:00
Bob Wilson
8190173350 For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap the
words within the 64-bit D registers.  Use VLD1/VST1 with 64-bit elements
instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107890 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 17:44:00 +00:00
Bob Wilson
8af4c54af1 Clean up a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107882 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 16:54:45 +00:00
Jakob Stoklund Olesen
0bc25f4040 Convert EXTRACT_SUBREG to COPY when emitting machine instrs.
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.

Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 16:40:22 +00:00