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199 Commits

Author SHA1 Message Date
Chris Lattner
e10038e54e callq is pcrelative 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98835 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-18 17:52:22 +00:00
Chris Lattner
4d82068167 fix the same bug on the x86-64 side of the fence. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98616 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-16 06:39:08 +00:00
Evan Cheng
700c71d2e8 Fix jit encoding bugs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98510 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-14 19:28:34 +00:00
Evan Cheng
f48ef03655 Do not force indirect tailcall through fixed registers: eax, r11. Add support to allow loads to be folded to tail call instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98465 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-14 03:48:46 +00:00
Daniel Dunbar
bf2d4c034d X86_64: Fix encoding for the rest of the 64i32 instructions too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98458 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-13 22:57:53 +00:00
Daniel Dunbar
859c9dc867 X86: Fix ADD64i32 encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98457 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-13 22:49:39 +00:00
Daniel Dunbar
96e2cec9c7 MC/X86_64: Fix matching of leaq. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98444 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-13 19:31:44 +00:00
Daniel Dunbar
989ac72981 MC/X86_64: Fix matching of callq. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98443 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-13 19:31:38 +00:00
Chris Lattner
341b27406d Correct immediate sizes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97957 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-08 18:55:15 +00:00
Chris Lattner
1840991d54 factor the 'sign extended from 8 bit' patterns better so 
that they are not destination type specific.  This allows
tblgen to factor them and the type check is redundant with
what the isel does anyway.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97629 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-03 01:45:01 +00:00
Dan Gohman
bc9d98b52d The mayHaveSideEffects flag is no longer used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-27 23:47:46 +00:00
Chris Lattner
4446c3f4d0 fix an incorrect (overly conservative) predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97316 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-27 08:18:55 +00:00
Chris Lattner
6d9f86b773 remove a bunch of dead named arguments in input patterns, 
though some look dubious afaict, these are all ok.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96899 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-23 06:54:29 +00:00
Chris Lattner
be5ad7dce2 fix a type mismatch in this pattern, where we were using an i64 imm in a 
place where an i32 imm was required, the old isel just got lucky.

This fixes CodeGen/X86/x86-64-and-mask.ll



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96894 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-23 06:09:57 +00:00
Chris Lattner
a599de2410 remove special cases for vmlaunch, vmresume, vmxoff, and swapgs 
fix swapgs to be spelled right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96058 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-13 00:41:14 +00:00
Daniel Dunbar
ccfa1db538 X86: Fix definition for RCL/RCR.*m? operations -- they were getting represented 
with "tied memory operands", which is wrong.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95950 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 01:22:03 +00:00
Chris Lattner
518bb53485 move target-independent opcodes out of TargetInstrInfo 
into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-09 19:54:29 +00:00
Chris Lattner
be1778fea7 really kill off the last MRMInitReg inst, remove logic from encoder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95437 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-05 21:34:18 +00:00
Chris Lattner
c74e333ecc factor code better in X86MCInstLower::Lower, teach it to 
lower the SETB* instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95431 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-05 21:13:48 +00:00
Evan Cheng
aa92bec010 Change TAILJMP's to be varargs and transfer implicit uses over from TCRETURN's. Otherwise the missing uses can make post-regalloc scheduling do bad things. This fixes 403.gcc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94950 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-31 07:28:44 +00:00
Daniel Dunbar
8a3ee718cd Mark EH_RETURN64 as CodeGenOnly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94205 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-22 20:16:37 +00:00
Evan Cheng
3bda20112e Eliminate or_not_add and just use AddedComplexity so isel tries or_is_add patterns first. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93245 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-12 18:31:19 +00:00
Dan Gohman
f1b4d26e67 Reapply the MOV64r0 patch, with a fix: MOV64r0 clobbers EFLAGS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93229 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-12 04:42:54 +00:00
Evan Cheng
199c4240fe Extend r93152 to work on OR r, r. If the source set bits are known not to overlap, then select as an ADD instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93191 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 22:03:29 +00:00
Evan Cheng
05920b8146 Revert 93158. It's breaking quite a few x86_64 tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93185 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 21:13:41 +00:00
Dan Gohman
e5dacc55ad Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it 
has an immediate with at least 32 bits of leading zeros, to avoid needing to
materialize that immediate in a register first.

FileCheckize, tidy, and extend a testcase to cover this case.

This fixes rdar://7527390.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93160 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 17:58:34 +00:00
Dan Gohman
71c25b7d7b Re-instate MOV64r0 and MOV16r0, with adjustments to work with the 
new AsmPrinter. This is perhaps less elegant than describing them
in terms of MOV32r0 and subreg operations, but it allows the
current register to rematerialize them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93158 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 17:37:57 +00:00
Dan Gohman
7e0d64a49c Pattern top-level operators don't need to be restricted to a 
single user. The _su forms are intended for non-top-level nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93155 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 17:21:05 +00:00
Evan Cheng
4b0345be30 Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93152 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 17:03:47 +00:00
Evan Cheng
b093bd0565 Fix what looks to me obvious instruction definition bugs. 
1. CMPXCHG8B and CMPXCHG16B did not specify implicit physical register defs and uses.
2. LCMPXCHG8B is loading 64 bit memory, not 32 bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92985 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-08 01:29:19 +00:00
Evan Cheng
760d1945bc Perform this folding as a target specific dag combine: 
(or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)

The isel patterns may not catch all the cases if general dag combine has reduced width of source operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92513 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-04 21:22:48 +00:00
Sean Callanan
108934c65d Instruction fixes, added instructions, and AsmString changes in the 
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 00:01:26 +00:00
Evan Cheng
2e489c4f9d Re-enable 91381 with fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91489 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-16 00:53:11 +00:00
Evan Cheng
dba6cac0d4 Fix an encoding bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91417 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 06:49:02 +00:00
Evan Cheng
ad9c0a3d8b Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91381 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 00:53:42 +00:00
Dan Gohman
22f6526081 Fix a minor inconsistency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90165 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-30 23:33:37 +00:00
Evan Cheng
6cccc30679 MOV64rm should be marked isReMaterializable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89019 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-17 00:55:55 +00:00
Anton Korobeynikov
3a639a07ea Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364. 
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85766 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 00:11:39 +00:00
Dan Gohman
f705adbe5e Initial x86 support for BlockAddresses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85557 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 01:28:02 +00:00
Dan Gohman
533297b58d Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-29 18:10:34 +00:00
Chris Lattner
172862a2a7 remove strings from instructions who are never asmprinted. 
All of these "subreg32" modifier instructions are handled
explicitly by the MCInst lowering phase.  If they got to
the asmprinter, they would explode.  They should eventually
be replace with correct use of subregs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84526 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 19:51:42 +00:00
Torok Edwin
6602922878 Fix PR5247, "lock addq" pattern (and other atomics), it DOES modify EFLAGS. 
LLC was scheduling compares before the adds causing wrong branches to be taken
in programs, resulting in misoptimized code wherever atomic adds where used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84485 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 11:00:58 +00:00
Dan Gohman
e220c4b3d9 Add support for using the FLAGS result of or, xor, and and instructions 
on x86, to avoid explicit test instructions. A few existing tests changed
due to arbitrary register allocation differences.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82263 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-18 19:59:53 +00:00
Sean Callanan
a2dc2825fc Added RCL and RCR (rotate left and right with a 
carry bit) instructions to the Intel instruction
tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82260 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-18 19:35:23 +00:00
Sean Callanan
9a86f10875 Added the LODS (load byte into register, usually 
as part string parsing) instructions to the Intel
instruction tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82089 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-16 22:59:28 +00:00
Sean Callanan
358f1ef765 Added the LAR (load segment access rights) 
instructions to the Intel instruction tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82084 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-16 21:55:34 +00:00
Sean Callanan
d2125a03af Added an alternate form of register-register CMP 
to the Intel instruction tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82081 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-16 21:11:23 +00:00
Sean Callanan
13cf8e9b82 Added the definitions for one-bit left shifts to 
the Intel instruction tables.

The patterns will stay blank because ADD reg, reg
is faster, but having the encoding available is
useful for the disassembler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81994 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-16 02:28:43 +00:00
Sean Callanan
62c28e3f91 Updated comments per Eli's suggestion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81923 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-15 21:43:27 +00:00
Sean Callanan
37be5903a6 Added register-to-register ADD instructions to the 
Intel tables, where the source operand is
specified by the R/M field and the destination
operand by the Reg field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81914 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-15 20:53:57 +00:00