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1264 Commits

Author SHA1 Message Date
Jim Grosbach
8050a61914 ARM parsing and encoding tests. 
UXTAB, UXTAB16, UXTAH, UXTB, UXTB16, and UXTH.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136312 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-28 00:37:03 +00:00
Evan Cheng
5de728cfe1 Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil. 
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.

rdar://8204588


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136292 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 23:22:03 +00:00
Jim Grosbach
ed398468b5 ARM assembly parsing and encoding for USUB16 and USUB8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136289 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 23:10:05 +00:00
Jim Grosbach
953e2e81de ARM assembly parsing and encoding for USAX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136288 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 23:07:00 +00:00
Kevin Enderby
c37d4bbf1f Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates. 
llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
    pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored.  The others remain unchanged.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136287 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 23:01:50 +00:00
Jim Grosbach
fc2eb31a3c Clean up tabs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136286 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:35:06 +00:00
Jim Grosbach
addec77b54 ARM assembly parsing and encoding support for USAT and USAT16. 
Use range checked immediate operands for instructions. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136285 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:34:17 +00:00
Jim Grosbach
5f33d13da4 ARM assembly parsing and encoding tests for USAD8 and USADA8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136284 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:23:02 +00:00
Jim Grosbach
144da2c8f0 ARM assembly parsing and encoding tests for UQSUB16 and UQSUB8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136282 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:13:08 +00:00
Jim Grosbach
41438398c1 Fix comment copy/paste-o. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136281 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:11:41 +00:00
Jim Grosbach
29e85bc728 ARM assembly parsing and encoding tests for UQASX and UQSAX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136280 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:09:30 +00:00
Jim Grosbach
24a541b79f ARM assembly parsing and encoding tests for UQADD16 and UQADD8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136279 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:08:14 +00:00
Jim Grosbach
49f2ceddd2 ARM assembly parsing and encoding for UMULL. 
Fix parsing of the 's' suffix for the mnemonic. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136277 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:01:42 +00:00
Jim Grosbach
71725a099e ARM assembly parsing and encoding for UMLAL. 
Fix parsing of the 's' suffix for the mnemonic. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136274 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 21:58:11 +00:00
Jim Grosbach
2adba4156b ARM assembly parsing and encoding tests for UMAAL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136272 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 21:53:42 +00:00
Jim Grosbach
f36b0a2ee4 ARM assembly parsing and encoding tests for UHSUB16 and UHSUB8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136267 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 21:21:59 +00:00
Jim Grosbach
66c8982244 ARM assembly parsing and encoding tests for UHADD16, UHADD8 and UHASX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136266 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 21:20:45 +00:00
Jim Grosbach
fb8989e640 ARM parsing and encoding of SBFX and UBFX. 
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 21:09:25 +00:00
Jim Grosbach
b6854ad2b1 ARM assembly parsing and encoding tests for UADD16, UADD8 and UASX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136261 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 20:43:44 +00:00
Jim Grosbach
8b3fd56e0f ARM assembly parsing and encoding tests for TST instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136260 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 20:38:58 +00:00
Jim Grosbach
f1ae78af17 ARM assembly parsing and encoding tests for TEQ instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136259 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 20:37:36 +00:00
Owen Anderson
06470311c5 Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136255 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 20:29:48 +00:00
Jim Grosbach
7e1547ebf7 ARM assembly parsing and encoding for extend instructions. 
Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136252 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 20:15:40 +00:00
Jim Grosbach
189610f946 ARM diagnostics for ldrexd/stredx out of order paired register operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136110 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 18:25:39 +00:00
Jim Grosbach
36711e4a3c ARM parsing and encoding tests for load/store exclusive instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136105 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 18:07:21 +00:00
Jim Grosbach
4f6f13db1a ARM assembly parsing and encoding for SWP[B] instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136098 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 17:15:11 +00:00
Jim Grosbach
ed8384806e ARM parsing and encoding for SVC instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136090 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 16:24:27 +00:00
Jim Grosbach
873db3eeba ARM assembly parsing and encoding tests for SUB instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136089 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 15:44:05 +00:00
Jim Grosbach
a46c658c66 Update ARM STM tests. Fix check: prefix for diagnostic tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136088 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 15:41:22 +00:00
Jim Grosbach
185f92e7d0 ARM assembly parsing and encoding for SSAX, SSUB16 and SSUB8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136013 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 23:32:14 +00:00
Jim Grosbach
f49433523e ARM assembly parsing and encoding for SSAT16 instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136006 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 23:09:14 +00:00
Jim Grosbach
580f4a9c1c ARM assembly parsing and encoding for SSAT instruction. 
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').

Add tests for diagnostics and proper encoding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135990 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 22:20:28 +00:00
Jim Grosbach
f2a35fbd60 Move some ELF directives into ELF asm parser. 
The .local, .hidden, .internal, and .protected are not legal for all supported
file formats (in particular, they're invalid for MachO). Move the parsing for
them into the ELF assembly parser since that's the format they're for.
Similarly, .weak is used by COFF and ELF, but not MachO, so move the parsing
to the COFF and ELF asm parsers. Previously, using any of these directives
on Darwin would result in an assertion failure in the parser; now we get
a diagnostic as we should.

rdar://9827089


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135921 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 17:55:35 +00:00
Jim Grosbach
6ab4e3dd23 Add FIXME 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135819 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 22:15:38 +00:00
Jim Grosbach
0e76edf8c0 ARM encoding and assembly parsing tests for SMULWB, SMULWT, SMUSD and SMUSDX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135818 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 22:13:00 +00:00
Jim Grosbach
bf2845c0d8 ARM assembly parsing and encoding updates. 
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135817 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 22:06:05 +00:00
Jim Grosbach
6808f21757 ARM assembly parsing and encoding tests. 
Add tests for SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR,
SMMUL, SMMULR, SMUAD and SMUADX.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135810 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 21:34:56 +00:00
Jim Grosbach
44a456332f ARM assembly parsing and encoding tests for SMLAWB/SMLAWT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135800 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 20:51:24 +00:00
Jim Grosbach
ce501030d9 ARM assembly parsing and encoding tests. 
Tests for SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, and SMLALDX
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135798 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 20:30:40 +00:00
Jim Grosbach
b544f68b70 ARM assembly parsing and encoding of SMLAL instruction. 
Fix parsing of carry-setting variant SMLALS and add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135797 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 20:18:21 +00:00
Jim Grosbach
b206daaec1 ARM encoding and assembly parsing of SMLAD{X} instructions. 
Fix encoding of destination register. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135796 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 20:11:20 +00:00
Jim Grosbach
0ffd4a09df ARM testcases for assembly parsing and encoding SMLA* instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135795 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 20:01:34 +00:00
Jim Grosbach
7c9fbc0340 ARM assembly parsing and encoding for SMC instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135782 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 18:13:31 +00:00
Jim Grosbach
248e6c328c ARM encoding and assembly parsing tests. 
Add tests for SHADD8, SHADD16, SHASX, SHSUB8, and SHSUB16.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135780 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 18:04:48 +00:00
Jim Grosbach
c27d4f9ea0 ARM assembly parsing and encoding for SETEND instruction. 
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135776 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 17:44:50 +00:00
Jim Grosbach
9076b6e8f4 ARM assembly parsing and encoding tests for SEL instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135772 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 16:59:33 +00:00
Jim Grosbach
8409f04731 ARM parsing and encoding tests for SBC instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135718 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 23:03:59 +00:00
Jim Grosbach
8ae45af794 ARM testcases for SADD/SASX parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135715 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 23:00:49 +00:00
Jim Grosbach
f790193aec ARM assembly parsing support for RSC instruction. 
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135713 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 22:56:30 +00:00
Jim Grosbach
86fdff0fa7 ARM assembly parsing support for RSB instruction. 
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135712 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-21 22:37:43 +00:00