Commit Graph

25668 Commits

Author SHA1 Message Date
Craig Topper
5bd1b815b3 Remove trailing whitespace and some tab characters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187472 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 02:00:15 +00:00
Craig Topper
1a5c55e54d Fixed incorrect disassembly for MOV16o16a when using Intel syntax.
Patch by Richard Mitton.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187471 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 01:50:26 +00:00
Akira Hatanaka
782638aa0d [mips] Rename instruction DANDi to ANDi64.
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187469 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 00:57:41 +00:00
Akira Hatanaka
52b7321a48 [mips] Define instruction itineraries IIArith and IILogic.
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187468 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 00:55:34 +00:00
Akira Hatanaka
80bec28b66 [mips] Delete instruction format for "bal".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187443 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-30 20:42:19 +00:00
Akira Hatanaka
8838da6587 [mips] Define "bal" as a pseudo instruction. Also, fix bug in the InstAlias that
turns "bal" into "bgezal".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187440 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-30 20:24:24 +00:00
Venkatraman Govindaraju
8717679c44 [Sparc] Rewrite MBB's live-in registers for leaf functions. Also, add
register i7 as a live-in if current function's return address is taken.

This revision fixes PR16269.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187433 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-30 19:53:10 +00:00
Tom Stellard
e3d60ac334 R600/SI: Expand vector fp <-> int conversions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187421 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-30 14:31:03 +00:00
Vladimir Medic
b67775df0c This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187410 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-30 10:12:14 +00:00
Saleem Abdulrasool
f7f22a64df [ARM] check bitwidth in PerformORCombine
When simplifying a (or (and B A) (and C ~A)) to a (VBSL A B C) ensure that the
bitwidth of the second operands to both ands match before comparing the negation
of the values.

Split the check of the value of the second operands to the ands.  Move the cast
and variable declaration slightly higher to make it slightly easier to follow.

Bug-Id: 16700
Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187404 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-30 04:43:08 +00:00
Venkatraman Govindaraju
80cdaf35ab [Sparc] Use call's debugloc for the unimp instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187402 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-30 02:26:29 +00:00
Bill Schmidt
646cd7933b [PowerPC] Skeletal FastISel support for 64-bit PowerPC ELF.
This is the first of many upcoming patches for PowerPC fast
instruction selection support.  This patch implements the minimum
necessary for a functional (but extremely limited) FastISel pass.  It
allows the table-generated portions of the selector to be created and
used, but in most cases selection will fall back to the DAG selector.
None of the block terminator instructions are implemented yet, and
most interesting instructions require some special handling.
Therefore there aren't any new test cases with this patch.  There will
be quite a few tests coming with future patches.

This patch adds the make/CMake support for the new code (including
tablegen -gen-fast-isel) and creates the FastISel object for PPC64 ELF
only.  It instantiates the necessary virtual functions
(TargetSelectInstruction, TargetMaterializeConstant,
TargetMaterializeAlloca, tryToFoldLoadIntoMI, and FastLowerArguments),
but of these, only TargetMaterializeConstant contains any useful
implementation.  This is present since the table-generated code
requires the ability to materialize integer constants for some
instructions.

This patch has been tested by building and running the
projects/test-suite code with -O0.  All tests passed with the
exception of a couple of long-running tests that time out using -O0
code generation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187399 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-30 00:50:39 +00:00
Quentin Colombet
15d1b85094 [R600] Replicate old DAGCombiner behavior in target specific DAG combine.
build_vector is lowered to REG_SEQUENCE, which is something the register
allocator does a good job at optimizing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187397 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-30 00:27:16 +00:00
Akira Hatanaka
c0fa31d51b [mips] Add comment and simplify function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187371 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-29 19:08:34 +00:00
Nico Rieck
fdbea5107b Use proper section suffix for COFF weak symbols
32-bit symbols have "_" as global prefix, but when forming the name of
COMDAT sections this prefix is ignored. The current behavior assumes that
this prefix is always present which is not the case for 64-bit and names
are truncated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187356 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-29 13:58:39 +00:00
Nico Rieck
944061c4e1 Proper va_arg/va_copy lowering on win64
Win64 uses CharPtrBuiltinVaList instead of X86_64ABIBuiltinVaList like
other 64-bit targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187355 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-29 13:07:06 +00:00
Silviu Baranga
fd79485dfa Allow generation of vmla.f32 instructions when targeting Cortex-A15. The patch also adds the VFP4 feature to Cortex-A15 and fixes the DontUseFusedMAC predicate so that we can still generate vmla.f32 instructions on non-darwin targets with VFP4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187349 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-29 09:25:50 +00:00
Robert Lytton
3d906e9846 test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187348 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-29 09:23:13 +00:00
Elena Demikhovsky
c18f4efc5d Added encoding prefixes for KNL instructions (EVEX).
Added 512-bit operands printing.
Added instruction formats for KNL instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187324 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-28 08:28:38 +00:00
Bill Schmidt
f5b9110ce1 [PowerPC] Add comment explaining preprocessor directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187320 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-28 03:23:32 +00:00
Bill Schmidt
eec21735b3 Revert 187318
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187319 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-28 02:13:24 +00:00
Bill Schmidt
8faa99081d [PowerPC] Remove unnecessary preprocessor checking.
The tests !defined(__ppc__) && !defined(__powerpc__) are not needed
or helpful when verifying that code is being compiled for a 64-bit
target.  The simpler test provided by this revision is sufficient to
tell if the target is 64-bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187318 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-28 02:08:13 +00:00
Chandler Carruth
214de30d9d Create a constant pool symbol for the GOT in the ARMCGBR the same way we
do in the SDag when lowering references to the GOT: use
ARMConstantPoolSymbol rather than creating a dummy global variable. The
computation of the alignment still feels weird (it uses IR types and
datalayout) but it preserves the exact previous behavior. This change
fixes the memory leak of the global variable detected on the valgrind
leak checking bot.

Thanks to Benjamin Kramer for pointing me at ARMConstantPoolSymbol to
handle this use case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187303 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-27 11:58:26 +00:00
Chandler Carruth
6c54b3dfb4 Fix yet another memory leak found by the vg-leak bot. Folks (including
me) should start watching this bot more as its catching lots of bugs.

The fix here is to not construct the global if we aren't going to need
it. That's cheaper anyways, and globals have highly predictable types in
practice. I've added an assert to catch skew between our manual testing
of the type and the actual type just for paranoia's sake.

Note that this pattern is actually fine in most globals because when you
build a global with a module it automatically is moved to be owned by
that module. But here, we're in isel and don't really want to do that.
The solution of not creating a global is simpler anyways.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187302 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-27 11:23:08 +00:00
Chandler Carruth
37886438dd Fix a memory leak in the hexagon scheduler. We call initialize here more
than once, and the second time through we leaked memory. Found thanks to
the vg-leak bot, but I can't locally reproduce it with valgrind. The
debugger confirms that it is in fact leaking here.

This whole code is totally gross. Why is initialize being called on each
runOnFunction??? Why aren't these OwningPtr<>s, and why aren't their
lifetimes better defined? Anyways, this is just a surgical change to
help out the leak checking bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187299 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-27 10:48:45 +00:00
Tom Stellard
57e6b2d1f3 SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions
Merge consecutive if-regions if they contain identical statements.
Both transformations reduce number of branches.  The transformation
is guarded by a target-hook, and is currently enabled only for +R600,
but the correctness has been tested on X86 target using a variety of
CPU benchmarks.

Patch by: Mei Ye

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187278 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-27 00:01:07 +00:00
Rafael Espindola
496cf2308a Revert "[PowerPC] Improve consistency in use of __ppc__, __powerpc__, etc."
This reverts commit r187248. It broke many bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187254 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 22:13:57 +00:00
Bill Schmidt
d063a326b2 [PowerPC] Improve consistency in use of __ppc__, __powerpc__, etc.
Both GCC and LLVM will implicitly define __ppc__ and __powerpc__ for
all PowerPC targets, whether 32- or 64-bit.  They will both implicitly
define __ppc64__ and __powerpc64__ for 64-bit PowerPC targets, and not
for 32-bit targets.  We cannot be sure that all other possible
compilers used to compile Clang/LLVM define both __ppc__ and
__powerpc__, for example, so it is best to check for both when relying
on either inside the Clang/LLVM code base.

This patch makes sure we always check for both variants.  In addition,
it fixes one unnecessary check in lib/Target/PowerPC/PPCJITInfo.cpp.
(At least one of __ppc__ and __powerpc__ should always be defined when
compiling for a PowerPC target, no matter which compiler is used, so
testing for them is unnecessary.)

There are some places in the compiler that check for other variants,
like __POWERPC__ and _POWER, and I have left those in place.  There is
no need to add them elsewhere.  This seems to be in Apple-specific
code, and I won't take a chance on breaking it.

There is no intended change in behavior; thus, no test cases are
added.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187248 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 21:39:15 +00:00
Akira Hatanaka
9758562aa7 [mips] Implement llvm.trap intrinsic.
Patch by Sasa Stankovic.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187244 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 20:58:55 +00:00
Akira Hatanaka
407883b69b [mips] Fix FP conditional move instructions to have explicit FP condition code
register operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187242 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 20:51:20 +00:00
Akira Hatanaka
83d8ef133b [mips] Fix FP branch instructions to have explicit FP condition code register
operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187238 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 20:13:47 +00:00
Akira Hatanaka
0fc641df37 [mips] Increase the number of floating point condition code registers to eight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187234 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 19:03:48 +00:00
Akira Hatanaka
9955cb931b [mips] Fix floating point branch, comparison, and conditional move instructions
to have register FCC0 (the first floating point condition code register) in
their Uses/Defs list.

No intended functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187233 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 19:01:56 +00:00
Akira Hatanaka
d6a7ea2736 [mips] Delete register print method MipsInstPrinter::printCPURegs that is not
needed. The generic method printOperand will do.

No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187231 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 18:50:42 +00:00
Akira Hatanaka
9b06dd6ca2 [mips] Print instructions "beq", "bne" and "or" using assembler pseudo
instructions "beqz", "bnez" and "move", when possible.

beq $2, $zero, $L1 => beqz $2, $L1
bne $2, $zero, $L1 => bnez $2, $L1
or  $2, $3, $zero  => move $2, $3



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 18:34:25 +00:00
Justin Holewinski
320185fa5f Add a target legalize hook for SplitVectorOperand (again)
CustomLowerNode was not being called during SplitVectorOperand,
meaning custom legalization could not be used by targets.

This also adds a test case for NVPTX that depends on this custom
legalization.

Differential Revision: http://llvm-reviews.chandlerc.com/D1195

Attempt to fix the buildbots by making the X86 test I just added platform independent

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187202 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 13:28:29 +00:00
Rafael Espindola
c735c1c2ae Revert "Add a target legalize hook for SplitVectorOperand"
This reverts commit 187198. It broke the bots.

The soft float test probably needs a -triple because of name differences.
On the hard float test I am getting a "roundss $1, %xmm0, %xmm0", instead of
"vroundss $1, %xmm0, %xmm0, %xmm0".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187201 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 13:18:16 +00:00
Justin Holewinski
5a24ed951b Add a target legalize hook for SplitVectorOperand
CustomLowerNode was not being called during SplitVectorOperand,
meaning custom legalization could not be used by targets.

This also adds a test case for NVPTX that depends on this custom
legalization.

Differential Revision: http://llvm-reviews.chandlerc.com/D1195

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187198 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 12:46:39 +00:00
Richard Osborne
c223ec731e test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187195 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 10:19:02 +00:00
Richard Osborne
21a8e31c9e [XCore] Add TODO regarding byval structs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187193 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 09:50:55 +00:00
Craig Topper
35786c0505 Fix more Intel syntax issues with FP instruction aliases. Test cases coming in a subsequent patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187187 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 05:37:46 +00:00
Craig Topper
b3053c528a Take advantage of the register enums being in order to remove a couple static tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187182 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 02:02:47 +00:00
Bill Schmidt
f38cc38fa6 [PowerPC] Support powerpc64le as a syntax-checking target.
This patch provides basic support for powerpc64le as an LLVM target.
However, use of this target will not actually generate little-endian
code.  Instead, use of the target will cause the correct little-endian
built-in defines to be generated, so that code that tests for
__LITTLE_ENDIAN__, for example, will be correctly parsed for
syntax-only testing.  Code generation will otherwise be the same as
powerpc64 (big-endian), for now.

The patch leaves open the possibility of creating a little-endian
PowerPC64 back end, but there is no immediate intent to create such a
thing.

The LLVM portions of this patch simply add ppc64le coverage everywhere
that ppc64 coverage currently exists.  There is nothing of any import
worth testing until such time as little-endian code generation is
implemented.  In the corresponding Clang patch, there is a new test
case variant to ensure that correct built-in defines for little-endian
code are generated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187179 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 01:35:43 +00:00
Roman Divacky
6ebf55d811 PPC32 va_list is an actual structure so va_copy needs to copy the whole
structure not just a pointer. This implements that and thus fixes va_copy
on PPC32. Fixes #15286. Both bug and patch by Florian Zeitz!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187158 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-25 21:36:47 +00:00
Rafael Espindola
6fccaafd8b Remove the mblaze backend from llvm.
Approval in here http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-July/064169.html

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187145 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-25 18:55:05 +00:00
Tim Northover
4632e31f51 AArch64: fix even more JIT failures
The last patch corrected some issues, but constant-pool entries had actual
codegen bugs in the large memory model (which MCJIT uses).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187126 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-25 16:03:54 +00:00
Richard Sandiford
ea14085be5 [SystemZ] Rework compare and branch support
Before the patch we took advantage of the fact that the compare and
branch are glued together in the selection DAG and fused them together
(where possible) while emitting them.  This seemed to work well in practice.
However, fusing the compare so early makes it harder to remove redundant
compares in cases where CC already has a suitable value.  This patch
therefore uses the peephole analyzeCompare/optimizeCompareInstr pair of
functions instead.

No behavioral change intended, but it paves the way for a later patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187116 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-25 09:34:38 +00:00
Richard Sandiford
bf99364f81 [SystemZ] Add LOCR and LOCGR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187113 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-25 09:11:15 +00:00
Richard Sandiford
cf20e45cc4 [SystemZ] Add LOC and LOCG
As with the stores, these instructions can trap when the condition is false,
so they are only used for things like (cond ? x : *ptr).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187112 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-25 09:04:52 +00:00
Richard Sandiford
b284e1bf08 [SystemZ] Add STOC and STOCG
These instructions are allowed to trap even if the condition is false,
so for now they are only used for "*ptr = (cond ? x : *ptr)"-style
constructs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187111 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-25 08:57:02 +00:00