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628b337561
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46159 Commits

Author SHA1 Message Date
Nick Lewycky
628b337561 No functionality change, just adjust some whitespace for coding style compliance. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128257 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 06:05:50 +00:00
Nick Lewycky
d56acb36ab No functionality change. Fix up some whitespace and switch out "" for '' when 
printing a single character.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128256 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 06:04:26 +00:00
Jakob Stoklund Olesen
eb5067e0d9 Ignore special ARM allocation hints for unexpected register classes. 
Add an assertion to linear scan to prevent it from allocating registers outside
the register class.

<rdar://problem/9183021>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128254 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 01:48:18 +00:00
Johnny Chen
a7078c4f27 Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed), 
modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128252 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 01:09:48 +00:00
Matt Beaumont-Gay
1866af4a98 Suppress an unused variable warning in -asserts builds 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128244 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 22:05:48 +00:00
Johnny Chen
c39b6271be Handle the added VBICiv*i* NEON instructions, too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128243 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 22:04:39 +00:00
Johnny Chen
8cb988686d Plug a leak by ThumbDisassembler::getInstruction(), thanks to Benjamin Kramer! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128241 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 21:42:55 +00:00
Johnny Chen
9091bf25d9 T2 Load/Store Multiple: 
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128240 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 21:36:56 +00:00
Benjamin Kramer
83ccbff84f Plug a leak in the arm disassembler and put the tests back. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128238 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 21:14:28 +00:00
Bruno Cardoso Lopes
505f3cd296 Add asm parsing support w/ testcases for strex/ldrex family of instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 21:04:58 +00:00
Johnny Chen
e6d69e7dbe ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled. 
Set the encoding bits to {0,?,?,0}, not 0.  Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128234 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 20:42:48 +00:00
Devang Patel
23670e5b95 Keep track of directory namd and fIx regression caused by Rafael's patch r119613. 
A better approach would be to move source id handling inside MC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128233 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 20:30:50 +00:00
Jim Grosbach
d31d304f83 Clean up assembly statement separator support. 
The MC asm lexer wasn't honoring a non-default (anything but ';') statement
separator. Fix that, and generalize a bit to support multi-character
statement separators.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128227 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 18:46:34 +00:00
Johnny Chen
b4ac342ea0 The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the 
VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function.  Add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128226 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 18:40:38 +00:00
Johnny Chen
ce1868b21c Add comments to the handling of opcode CPS3p to reject invalid instruction encoding, 
a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128220 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 17:04:22 +00:00
Andrew Trick
0a828fd7ef revert r128199 until it can be made to work with Frontend/dependency-gen.c. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128218 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 16:43:37 +00:00
Cameron Zwarich
9035484200 Debug intrinsics must be skipped at the beginning and ends of blocks, lest they 
affect the generated code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128217 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 16:34:59 +00:00
Cameron Zwarich
dc31cfeb74 It is enough for the CallInst to have no uses to be made a tail call with a ret 
void; it doesn't need to have a void type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128212 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 15:54:11 +00:00
Devang Patel
52e37df8c0 s/UpdateDT/ModifiedDT/g 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128211 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 15:35:25 +00:00
NAKAMURA Takumi
a2e0762fae Target/X86: [PR8777][PR8778] Tweak alloca/chkstk for Windows targets. 
FIXME: Some cleanups would be needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128206 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 07:07:00 +00:00
Evan Cheng
d700617193 Nasty bug in ARMBaseInstrInfo::produceSameValue(). The MachineConstantPoolEntry 
entries being compared may not be ARMConstantPoolValue. Without checking
whether they are ARMConstantPoolValue first, and if the stars and moons
are aligned properly, the equality test may return true (when the first few
words of two Constants' values happen to be identical) and very bad things can
happen.

rdar://9125354


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128203 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 06:20:03 +00:00
Michael J. Spencer
e1db1b8d4e Remove all uses of PATH_MAX and MAXPATHLEN from PathV2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128199 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 05:23:40 +00:00
Cameron Zwarich
6e8ffc1c4d Do early taildup of ret in CodeGenPrepare for potential tail calls that have a 
void return type. This fixes PR9487.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128197 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 04:52:10 +00:00
Cameron Zwarich
4bae588c75 Use an early return instead of a long if block. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128196 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 04:52:07 +00:00
Cameron Zwarich
680c962ebd When UpdateDT is set, DT is invalid, which could cause problems when trying to 
use it later. I couldn't make a test that hits this with the current code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128195 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 04:52:04 +00:00
Cameron Zwarich
661a390b83 Check for TLI so that -codegenprepare can be used from opt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128194 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 04:51:51 +00:00
Johnny Chen
e4000595fb CPS3p: Let's reject impossible imod values by returning false from the DisassembleMiscFrm() function. 
Fixed rdar://problem/9179416 ARM disassembler crash: "Unknown imod operand" (fuzz testing)

Opcode=98 Name=CPS3p Format=ARM_FORMAT_MISCFRM(26)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

Before:
	cpsUnknown imod operand
UNREACHABLE executed at /Volumes/data/lldb/llvm/lib/Target/ARM/InstPrinter/../ARMBaseInfo.h:123!

After:
/Volumes/data/Radar/9179416/mc-input-arm.txt:1:1: warning: invalid instruction encoding
0x93 0x1c 0x2 0xf1
^


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128192 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 02:24:36 +00:00
Johnny Chen
3d793962be Load/Store Multiple: 
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add two test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128191 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 01:40:42 +00:00
Johnny Chen
571f290376 STRT and STRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821). 
We now tag them as IndexModePost.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 01:07:26 +00:00
Johnny Chen
2abc9d2444 The r128103 fix to cope with the removal of addressing modes from the MC instructions 
were incomplete.  The assert stmt needs to be updated and the operand index incrment is wrong.
Fix the bad logic and add some sanity checking to detect bad instruction encoding;
and add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128186 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 00:28:38 +00:00
Jim Grosbach
5ffe37f2c7 Runtime dylib simple ARM 24-bit branch relocation support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128184 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 23:35:17 +00:00
Devang Patel
36dca60f5c Enable GlobalMerge on darwin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128183 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 23:34:19 +00:00
Andrew Trick
f6c39412dd Revert r128175. 
I'm backing this out for the second time. It was supposed to be fixed by r128164, but the mingw self-host must be defeating the fix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128181 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 23:11:02 +00:00
Evan Cheng
2c33915628 Cmp peephole optimization isn't always safe for signed arithmetics. 
int tries = INT_MAX;    
while (tries > 0) {
      tries--;
}

The check should be:
        subs    r4, #1
        cmp     r4, #0
        bgt     LBB0_1

The subs can set the overflow V bit when r4 is INT_MAX+1 (which loop
canonicalization apparently does in this case). cmp #0 would have cleared
it while not changing the N and Z bits. Since BGT is dependent on the V
bit, i.e. (N == V) && !Z, it is not safe to eliminate the cmp #0.

rdar://9172742


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128179 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 22:52:04 +00:00
Eli Friedman
b141099c14 PR9535: add support for splitting and scalarizing vector ISD::FP_ROUND. 
Also cleaning up some duplicated code while I'm here.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128176 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 22:18:48 +00:00
Andrew Trick
d8fa01fbd7 Reapply Eli's r127852 now that the pre-RA scheduler can spill EFLAGS. 
(target-specific branchless method for double-width relational comparisons on x86)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128175 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 22:16:02 +00:00
Jim Grosbach
a8287e322f Split out relocation resolution into target-specific bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128173 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 22:06:06 +00:00
Owen Anderson
741ad15e26 The high bit of a Thumb2 ADR's offset is stored in bit 26, not bit 25. 
This fixes 464.h264ref with the integrated assembler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128172 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 22:03:44 +00:00
Jim Grosbach
66978bd81c Fix double-free of Module. 
The ExecutionEngine constructor already added the module, so there's no
need to call addModule() directly. Doing so causes a double-free of the
Module at program termination.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128171 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 21:35:02 +00:00
Owen Anderson
7614783f2d Fix a bug introduced by my patch yesterday: BL is a 4-byte instructions like BLX, rather than a 2-byte instruction like B. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128169 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 21:19:56 +00:00
Andrew Trick
bd47a4a307 Ensure that def-side physreg copies are scheduled above any other uses 
so the scheduler can't create new interferences on the copies
themselves. Prior to this fix the scheduler could get stuck in a loop
creating copies.
Fixes PR9509.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128164 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 20:42:39 +00:00
Andrew Trick
0d93a110e3 whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128163 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 20:40:18 +00:00
Jim Grosbach
8b54dca41c Start of relocation resolution for the runtime dyld library. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128161 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 19:52:00 +00:00
Jim Grosbach
8086f3b494 Make sure to report any errors from the runtime dyld. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128160 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 19:51:34 +00:00
Jakob Stoklund Olesen
01079311e1 Don't coalesce identical DBG_VALUE instructions prematurely. 
Each of these instructions may have a RegsClobberInsn entry that can't be
ignored. Consecutive ranges are coalesced later when DwarfDebug::emitDebugLoc
merges entries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128155 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 18:37:30 +00:00
Justin Holewinski
d662576671 PTX: Improve support for 64-bit addressing 
- Fix bug in ADDRrr/ADDRri/ADDRii selection for 64-bit addresses
- Add comparison selection for i64
- Add zext selection for i32 -> i64
- Add shl/shr/sha support for i64

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128153 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 16:58:51 +00:00
Anders Carlsson
fa4ebd396d Revert r128140 for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128149 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 15:51:12 +00:00
Cameron Zwarich
1537ce75ed Fix PR9464 by correcting some math that just happened to be right in most cases 
that were hit in practice.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128146 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 05:25:55 +00:00
Jakob Stoklund Olesen
1e6c65dba7 Notify the delegate before removing dead values from a live interval. 
The register allocator needs to know when the range shrinks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128145 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 04:43:16 +00:00
Jakob Stoklund Olesen
0b5015188e Allow the allocation of empty live ranges that have uses. 
Empty ranges may represent undef values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128144 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 04:32:51 +00:00