Saleem Abdulrasool
632c1e5eb6
ARM: style changes to LDRD, STRD definition
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Fix indentation, name registers similar to ARM ARM.
No functionality change!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198563 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-05 16:36:37 +00:00
Elena Demikhovsky
497417520c
AVX-512: changed property name from "neverHasSideEffects=1" to "hasSideEffects=0", added this property to VMOVSS/VMOVSD;
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Optimized a truncate pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198562 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-05 14:21:07 +00:00
Elena Demikhovsky
3a880de6e6
AVX-512: Added more intrinsics for convert and min/max.
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Removed vzeroupper from AVX-512 mode - our optimization gude does not recommend to insert vzeroupper at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198557 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-05 10:46:09 +00:00
Craig Topper
9005d2a842
Add the other form of movq xmm,xmm for the disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198551 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-05 07:16:04 +00:00
Craig Topper
adb7d3b49b
Use patterns to remove some duplicate instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198550 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-05 06:55:48 +00:00
Craig Topper
6a69266fed
Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198547 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-05 05:46:38 +00:00
Craig Topper
01cb7fa977
Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198545 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-05 04:55:55 +00:00
Craig Topper
2b5dc93948
Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode and remove disassmbler table emitter hack.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198544 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-05 04:32:42 +00:00
Craig Topper
527f132627
Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198543 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-05 04:17:28 +00:00
Venkatraman Govindaraju
5d02c84191
[Sparc] Add initial implementation of MC Code emitter for sparc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198533 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-05 02:13:48 +00:00
Bill Wendling
4a816471f5
Emit an error message if the value passed to __builtin_returnaddress isn't a constant
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__builtin_returnaddress requires that the value passed into is be a constant.
However, at -O0 even a constant expression may not be converted to a constant.
Emit an error message intead of crashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198531 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-05 01:47:20 +00:00
Craig Topper
e43a0f8015
Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198530 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-05 01:35:51 +00:00
Craig Topper
29d56f68c6
Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. Remove disassembler hack.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198515 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-04 22:29:41 +00:00
Venkatraman Govindaraju
72d2b05254
[Sparc] Add the initial implementation of an asm parser for sparc/sparcv9.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198484 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-04 11:30:13 +00:00
Venkatraman Govindaraju
6e202a960e
[SparcV9]: Implement RETURNADDR and FRAMEADDR lowering in SPARC64.
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Fixes PR18356.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198480 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-04 07:17:21 +00:00
Craig Topper
030ceadd69
Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198475 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-04 05:09:27 +00:00
Rafael Espindola
8e0f67dcec
Make the llvm mangler depend only on DataLayout.
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Before this patch any program that wanted to know the final symbol name of a
GlobalValue had to link with Target.
This patch implements a compromise solution where the mangler uses DataLayout.
This way, any tool that already links with Target (llc, clang) gets the exact
behavior as before and new IR files can be mangled without linking with Target.
With this patch the mangler is constructed with just a DataLayout and DataLayout
is extended to include the information the Mangler needs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198438 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-03 19:21:54 +00:00
Ana Pazos
5124fef085
[AArch64][NEON] Added SXTL and SXTL2 instruction aliases
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198437 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-03 19:20:31 +00:00
Hal Finkel
79d8722b11
[PPC] Fix comment to match function name
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198362 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-02 22:09:39 +00:00
Hal Finkel
d151389bd1
[PPC] Fix the scheduling of CR logicals on the P7
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CR logicals (crand, crxor, etc.) on the P7 need to be in the first slot of each
dispatch group. The old itinerary entry was just wrong (but has not mattered
because we don't generate these instructions).
This will matter when, in an upcoming commit, we start generating these
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198359 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-02 21:38:26 +00:00
Hal Finkel
73a5fdd886
[PPC] Use the correct immediate operands on 64-bit instructions
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Several of the 64-bit fixed-point instructions with immediate operands were
using the 32-bit (i32) operand nodes instead of the corresponding 64-bit (i64)
operand definitions (u16imm instead of u16imm64, for example).
This error has had no effect so far, but would have caused type-checking
violations with an upcoming change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198356 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-02 21:26:59 +00:00
Craig Topper
d573aba8e1
Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198336 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-02 19:12:10 +00:00
Craig Topper
a7133ee752
Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack from the disassembler table builder.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198327 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-02 18:20:48 +00:00
Craig Topper
e625100c6a
Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler table builder doesn't need to string match them to exclude them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198323 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-02 17:28:14 +00:00
Logan Chien
311730494e
[arm] Add softvfp to supported FPU names.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198313 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-02 15:50:02 +00:00
Rafael Espindola
a21a8a863d
Make the ARM ABI selectable via SubtargetFeature.
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This patch makes it possible to select the ABI with -mattr. It will be used to
forward clang's -target-abi option to llvm's CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198304 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-02 13:40:08 +00:00
Rafael Espindola
33cc3f81c1
Remove the 's' DataLayout specification
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During the years there have been some attempts at figuring out how to
align byval arguments. A look at the commit log suggests that they
were
* Use the ABI alignment.
* When that was not sufficient for x86-64, I added the 's' specification to
DataLayout.
* When that was not sufficient Evan added the virtual getByValTypeAlignment.
* When even that was not sufficient, we just got the FE to add the alignment
to the byval.
This patch is just a simple cleanup that removes my first attempt at fixing the
problem. I also added an AArch64 implementation of getByValTypeAlignment to
make sure this patch is a nop. I also left the 's' parsing for backward
compatibility.
I will send a short email to llvmdev about the change for anyone maintaining
an out of tree target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198287 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-01 22:29:43 +00:00
Venkatraman Govindaraju
447c3480e5
[Sparc] Handle atomic loads/stores in sparc backend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198286 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-01 22:11:54 +00:00
Craig Topper
5cfd40ccd4
Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198284 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-01 21:52:57 +00:00
Venkatraman Govindaraju
924ac6dc0c
[SparcV9]: Custom lower UMULO/SMULO so that the arguments are send to __multi3() in correct order.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198281 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-01 20:22:45 +00:00
Venkatraman Govindaraju
ca0ef6fe4f
[SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL does not clear top 32 bit, only SRL does.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198280 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-01 19:00:10 +00:00
NAKAMURA Takumi
550848ecb9
X86Disassembler.cpp: Prune stray @return on translateFPRegister(). [-Wdocumentation]
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198279 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-01 16:19:26 +00:00
Craig Topper
95a3ccdd80
Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198278 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-01 15:29:32 +00:00
Elena Demikhovsky
3062a311ac
AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp
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Printing rounding control.
Enncoding for EVEX_RC (rounding control).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198277 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-01 15:12:34 +00:00
Craig Topper
979b2cd2bc
Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198276 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-01 14:22:37 +00:00
Craig Topper
5cbbd7e1a5
Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198265 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-31 17:21:44 +00:00
Craig Topper
31b27056a6
Remove old comment referring to an argument that no longer exists.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198263 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-31 15:29:14 +00:00
Mark Seaborn
56b7f736a6
Fix misaligned indentation in "if" block in MipsMCCodeEmitter.cpp
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198262 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-31 13:05:15 +00:00
Craig Topper
c46a29cd9c
Add missing MRM_XX forms to the old JIT emitter for consistency.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198258 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-31 03:26:24 +00:00
Craig Topper
64f275b59c
Remove MRMInitReg form now that it's last use is gone.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198257 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-31 03:19:03 +00:00
Craig Topper
ec62c1ae99
Handle MOV32r0 in expandPostRAPseudo instead of MCInst lowering. No functional change intended.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198254 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-31 03:05:38 +00:00
Craig Topper
ad5e4b9476
Merge case statements to remove redundant code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198241 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 19:47:49 +00:00
Craig Topper
e6d2dce7ab
Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198238 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 19:16:48 +00:00
Saleem Abdulrasool
4ba4132d62
ARM IAS: account for predicated pre-UAL mnemonics
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Checking the trailing letter of the mnemonic is insufficient. Be more thorough
in the scanning of the instruction to ensure that we correctly work with the
predicated mnemonics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198235 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 18:38:01 +00:00
Bill Wendling
8e58e03822
Keep comment with 'Subtarget' ivar.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198201 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 05:17:29 +00:00
Jiangning Liu
90128bee68
For AArch64 Neon, simplify scalar dup by lane0 for fp.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198194 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 02:44:35 +00:00
Hao Liu
afcdbf7400
[AArch64]Add code to spill/fill Q register tuples such as QPair/QTriple/QQuad.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198193 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 02:38:12 +00:00
Hao Liu
43ffcc571c
[AArch64]Can't select shift left 0 of type v1i64
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198192 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 02:12:46 +00:00
Hao Liu
3796015b5b
[AArch64]Fix the problem that can't select mul of v1i64/v2i64 types.
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E.g. Can't select such IR:
%tmp = mul <2 x i64> %a, %b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198188 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 01:38:41 +00:00
Saleem Abdulrasool
ee6d3cd701
ARM IAS: fix after r198172
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The DPR and SPR register lists are also register lists. Furthermore, the
registers need not be checked individually since the register type can be
checked via the list kind. Use that to simplify the logic and fix the incorrect
assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198174 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-29 18:53:16 +00:00