Commit Graph

3688 Commits

Author SHA1 Message Date
Jay Foad
b33f8e3e55 Merge gtest-1.6.0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136212 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 09:25:14 +00:00
Owen Anderson
793e79601f Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136141 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 20:54:26 +00:00
Jim Grosbach
ed8384806e ARM parsing and encoding for SVC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136090 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 16:24:27 +00:00
Evan Cheng
94b9550a32 Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 00:24:13 +00:00
Jim Grosbach
f49433523e ARM assembly parsing and encoding for SSAT16 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136006 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 23:09:14 +00:00
Benjamin Kramer
a397a11c7c We always bounds check the bit set, there is no need to emit zero bytes at the end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135841 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-23 02:49:37 +00:00
Benjamin Kramer
9df8567548 Turn the DenseSet in MCRegisterClass into a tblgenerated bit field. This should be faster and smaller.
Goodbye static ctors and dtors!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135836 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-23 00:47:49 +00:00
Benjamin Kramer
f496d68493 Give TargetRegisterClass a pointer to the MCRegisterClass and use it to access its data.
This makes TargetRegisterClass slightly slower. Next step will be making contains faster.
Eventually TargetRegisterClass will be killed entirely.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135835 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-23 00:47:46 +00:00
Jim Grosbach
4a5ffb399f ARM SSAT instruction 5-bit immediate handling.
The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135823 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 23:16:18 +00:00
Benjamin Kramer
256535f136 Use the enum value for RegClassIDs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135816 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 22:01:58 +00:00
Benjamin Kramer
c848066843 Remove unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135768 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 16:06:09 +00:00
Benjamin Kramer
8ca9a86203 Teach tblgen to emit MCRegisterClasses.
- This currently introduces more instances of the static DenseSet dtor, but that should be fixable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135735 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 00:44:39 +00:00
Owen Anderson
152d4a4bb6 Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135722 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 23:38:37 +00:00
Owen Anderson
92a202213b Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135693 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 18:54:16 +00:00
Chris Lattner
c30a38f34b move tier out of an anonymous namespace, it doesn't make sense
to for it to be an an anon namespace and be in a header.

Eliminate some extraenous uses of tie.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135669 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 06:21:31 +00:00
Jim Grosbach
dde038af59 ARM PKH shift ammount operand printing tweaks.
Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0" and prepares for correct asm parsing of these
operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135626 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 21:40:26 +00:00
Owen Anderson
f1a0090073 Enhance the FixedLengthDecoder to be able to generate plausible-looking decoders for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135524 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 21:06:00 +00:00
Jim Grosbach
ffa3225e26 ARM assembly parsing for MOV (immediate).
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135500 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 19:13:28 +00:00
Owen Anderson
565a036697 Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having multiple instructions with the same encoding. This resolves another conflict when bringing up the new-style disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135442 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18 23:25:34 +00:00
Evan Cheng
0e6a052331 Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down
to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18 20:57:22 +00:00
Owen Anderson
0af0dc8ac6 Re-apply r135319 with a fix for the constant island pass.
Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode.  Update the ARM disassembler for this change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135414 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18 18:50:52 +00:00
Jakob Stoklund Olesen
77f8274c7d Intern all RecTy subclass instances to avoid duplicates.
Make all of the RecTy constructors private, and use get() factory
methods instead. Return singleton instances when it makes sense.

ListTy instance pointers are stored in the element RecTy instance.

BitsRecTy instance pointers, one per length, are stored in a static vector.

Also unique DefInit instances. A Record has a unique DefInit which
has a unique RecordRecTy instance.

This saves some 200k-300k RecTy allocations when parsing ARM.td. It
reduces TableGen's heap usage by almost 50%.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135399 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18 17:02:57 +00:00
Frits van Bommel
39b5abf507 Migrate LLVM and Clang to use the new makeArrayRef(...) functions where previously explicit non-default constructors were used.
Mostly mechanical with some manual reformatting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135390 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18 12:00:32 +00:00
Owen Anderson
91ddfc4723 Revert r135319 in an attempt to get to unbreak testers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135343 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-16 09:17:43 +00:00
Eli Friedman
7105259ce8 Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-16 02:41:28 +00:00
Owen Anderson
49e163b6c7 Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135319 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-15 22:49:31 +00:00
Kevin Enderby
893818347e Have tblgen produce code that tolerates operands that return an invalid match class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135287 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-15 18:30:43 +00:00
NAKAMURA Takumi
20722b6cda Eliminate "const" from extern const to fix breakeage since r135184 on msvc.
MSVC decorates (and distinguishes) "const" in mangler. It brought linkage error between "extern const" declarations and definitions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135269 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-15 12:50:21 +00:00
Benjamin Kramer
5196c12e9f Add a new field to MCOperandInfo that contains information about the type of the Operand.
- The actual values are from the MCOI::OperandType enum.
- Teach tblgen to read it from the instruction definition.
- This is a better implementation of the hacks in edis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135197 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 21:47:18 +00:00
Evan Cheng
c60f9b7523 Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 20:59:42 +00:00
Chris Lattner
154c535888 though it isn't the case here, the key of a StringMap can
conceptually have nuls in it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135165 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 18:21:58 +00:00
Benjamin Kramer
eb9a85f09e Change Intrinsic::getDeclaration and friends to take an ArrayRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135154 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 17:45:39 +00:00
Owen Anderson
16884415db Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 23:22:26 +00:00
David Greene
afd54269ab struct Init -> class Init
Rename struct Init to class Init for consistency and in preparation
for making Init a FoldingSetNode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135097 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:25:51 +00:00
Jim Grosbach
83ab070fc1 Range checking for CDP[2] immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:01:08 +00:00
Jim Grosbach
619e0d6d95 Give the ARM BKPT instruction the right operand type.
The immediate is of limited range and the operand type should reflect that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135066 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 19:24:09 +00:00
Eric Christopher
d568b3f552 Revert r134921, 134917, 134908 and 134907. They're causing failures
in multiple buildbots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 23:06:52 +00:00
David Greene
5e3cb47bea Use get(0 Instead of Create()
Respond to some feedback asking for a name change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 20:55:22 +00:00
Evan Cheng
9bcc399f1c struct Init -> class Init.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134917 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 20:23:13 +00:00
David Greene
1bb6e28ac2 Fix Build
Update the tag for Init to match how it's defined.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134908 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 18:59:29 +00:00
David Greene
d4a9066c93 [AVX] Make Inits Foldable
Manage Inits in a FoldingSet.  This provides several benefits:

- Memory for Inits is properly managed

- Duplicate Inits are folded into Flyweights, saving memory

- It enforces const-correctness, protecting against certain classes
  of bugs

The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen.  This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134907 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 18:25:51 +00:00
Shantonu Sen
7ae0df4142 Resynchronize EDInfo.h and EDEmitter.cpp.
The enum names as well as order (i.e. value)
had skewed, which means that consumers of the
tablegen-ed table would see different values than
intended. Make both files have a superset of enums,
and add classification as needed for numMCOperands.

Reviewed by Owen Anderson


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134905 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 17:57:30 +00:00
Evan Cheng
59ee62d241 - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 03:57:24 +00:00
NAKAMURA Takumi
6bb5fe3a0d lit/LitConfig.py: Demote Win32 message "Unable to find 'bash.exe'" from Warning to Note.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134809 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 07:19:50 +00:00
Eli Friedman
6043548bfe Fix dangling pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134725 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 20:07:05 +00:00
Evan Cheng
fbc38d2c16 Fix a dangling reference. Patch by Dave Abrahams. pr10311
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134709 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 18:04:22 +00:00
Jim Grosbach
86f9adb8be TableGen'erated MC lowering for simple pseudo-instructions.
This allows the (many) pseudo-instructions we have that map onto a single
real instruction to have their expansion during MC lowering handled
automatically instead of the current cumbersome manual expansion required.
These sorts of pseudos are common when an instruction is used in situations
that require different MachineInstr flags (isTerminator, isBranch, et. al.)
than the generic instruction description has. For example, using a move
to the PC to implement a branch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134704 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 17:36:35 +00:00
Evan Cheng
ebdeeab812 Eliminate asm parser's dependency on TargetMachine:
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
  to generate asm matcher subtarget feature queries. e.g.
  "ModeThumb,FeatureThumb2" is translated to
  "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134678 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 01:53:10 +00:00
Evan Cheng
0ddff1b535 Compute feature bits at time of MCSubtargetInfo initialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134606 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 07:07:08 +00:00
Jim Grosbach
e727d67c58 Add isCodeGenOnly value to the CodeGenInstruction class.
So users of a CGI don't have to look up the value directly from the original
Record; just like the rest of the convenience values in the class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134576 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 00:48:02 +00:00
Jim Grosbach
66c9ee7e6d Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134563 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 23:38:13 +00:00
Jim Grosbach
806fcc040e Don't require pseudo-instructions to carry encoding information.
For now this is distinct from isCodeGenOnly, as code-gen-only
instructions can (and often do) still have encoding information
associated with them. Once we've migrated all of them over to true
pseudo-instructions that are lowered to real instructions prior to
the printer/emitter, we can remove isCodeGenOnly and just use isPseudo.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134539 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 21:33:38 +00:00
David Greene
e234cd9717 Allow tagless builds and fix debug build configuration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134498 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 16:54:14 +00:00
Evan Cheng
68ae5b4bea Remove the AsmWriterEmitter (unused) feature that rely on TargetSubtargetInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134457 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 02:02:33 +00:00
Jordy Rose
2f494b6afc Use subprocess.Popen instead of popen2 to stop a deprecation warning when running lit on OS X
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134324 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02 17:28:55 +00:00
Evan Cheng
5b1b4489cf Rename TargetSubtarget to TargetSubtargetInfo for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134259 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 21:01:15 +00:00
Evan Cheng
94214703d9 - Added MCSubtargetInfo to capture subtarget features and scheduling
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
  and hide more details from targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134257 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 20:45:01 +00:00
Evan Cheng
4db3cffe94 Hide the call to InitMCInstrInfo into tblgen generated ctor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 17:57:27 +00:00
Jim Grosbach
ff97eb0cf4 Pseudo-ize the Thumb tTPsoft instruction.
It's just a call to a special helper function. Get rid of the T2 variant
entirely, as it's identical to the Thumb1 version.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134178 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30 19:38:01 +00:00
Jim Grosbach
4629d50501 Pseudo-ize the Thumb tPOP_RET instruction.
It's just a tPOP instruction with additional code-gen properties, so it
doesn't need encoding information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134172 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30 17:34:04 +00:00
Evan Cheng
276365dd4b Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to
be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.

The fix is to just have the clients explictly pass the CPU name!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134127 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30 01:53:36 +00:00
Jim Grosbach
f6fd90910a Remove redundant Thumb2 ADD/SUB SP instruction definitions.
Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the
stack pointer. It can just use the normal add-register-immediate encoding
since it can use all registers as a source, not just R0-R7. The extra
instruction definitions are just duplicates of the normal instructions with
the (not well enforced) constraint that the source register was SP.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134114 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29 23:25:04 +00:00
Jim Grosbach
ae218dee5e ARM RSCS* don't need explicit TableGen decoder checks.
They've been pseudos for a while now, so the decoder will never see
them in the first place.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134101 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29 22:01:15 +00:00
Jim Grosbach
74472b4bf9 Refactor away tSpill and tRestore pseudos in ARM backend.
The tSpill and tRestore instructions are just copies of the tSTRspi and
tLDRspi instructions, respectively. Just use those directly instead.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134092 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29 20:26:39 +00:00
Francois Pichet
2e10b08744 Change AsmName's type from StringRef to std::string. AsmName was pointing to a temporary string object that was destroyed. This is undefined behavior and MSVC didn't like it.
This fixes over 300+ failing tests on MSVC.
Credit for this fix goes to chapuni.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29 11:25:34 +00:00
Evan Cheng
ab8be96fd3 Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134049 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29 01:14:12 +00:00
Evan Cheng
d5b03f252c Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134030 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 21:14:33 +00:00
Evan Cheng
6844f7bcde Hide more details in tablegen generated MCRegisterInfo ctor function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 20:44:22 +00:00
Evan Cheng
94b01f6882 Add MCInstrInfo registeration machinery.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 20:29:03 +00:00
Evan Cheng
22fee2dff4 Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 20:07:07 +00:00
Evan Cheng
e837dead3c - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 19:10:37 +00:00
Evan Cheng
4987033fbd Alternative name enum should go into the enum portion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133979 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 01:36:01 +00:00
Jim Grosbach
6b8f1e35ea ARM Assembly support for Thumb mov-immediate.
Correctly parse the forms of the Thumb mov-immediate instruction:
  1. 8-bit immediate 0-255.
  2. 12-bit shifted-immediate.

The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic,
but is not yet supported. More parser logic necessary there due to fixups.


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2011-06-27 23:54:06 +00:00
Evan Cheng
4db3748fcf Remove RCBarriers from TargetInstrDesc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133964 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 23:47:21 +00:00
Owen Anderson
bea6f615ee Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0.
Patch by Jim Grosbach.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133940 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 21:06:21 +00:00
Evan Cheng
ebbbfd0e2e More refactoring. MC doesn't need know about subreg indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133927 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 19:24:13 +00:00
Evan Cheng
73f50d9bc3 Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc
into XXXGenRegisterInfo.inc.


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2011-06-27 18:32:37 +00:00
Evan Cheng
025b37b5f0 Remove dead typedefs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133851 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-25 00:27:17 +00:00
Evan Cheng
5e6b4605bd Rename TargetRegisterDesc to MCRegisterDesc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133845 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 23:44:48 +00:00
Bob Wilson
9c99cfef93 Revert "Shorten some ARM builtin names by removing unnecessary "neon" prefix."
Sorry, this was a bad idea.  Within clang these builtins are in a separate
"ARM" namespace, but the actual builtin names should clearly distinguish that
they are target specific.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133832 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 22:13:17 +00:00
Bob Wilson
e9e0e3aeaf Shorten some ARM builtin names by removing unnecessary "neon" prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133825 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 21:32:40 +00:00
Evan Cheng
f5fa52ed06 - Add MCRegisterInfo registration machinery. Also added x86 registration routines.
- Rename TargetRegisterDesc to MCRegisterDesc.


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2011-06-24 20:42:09 +00:00
Benjamin Kramer
5c10b63969 Make the generated InitXXXMCRegisterInfo function "static inline", so it doesn't get emitted into multiple object files.
This caused linker errors when linking both libLLVMX86Desc and libLLVMX86CodeGen
into a single binary (for example when building a monolithic libLLVM shared library).

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2011-06-24 11:03:31 +00:00
Evan Cheng
a347f85dbe Starting to refactor Target to separate out code that's needed to fully describe
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24 01:44:41 +00:00
Andrew Trick
f2a58425cd lit support for REQUIRES: asserts.
Take #2. Don't piggyback on the existing config.build_mode. Instead,
define a new lit feature for each build feature we need (currently
just "asserts"). Teach both autoconf'd and cmake'd Makefiles to define
this feature within test/lit.site.cfg. This doesn't require any lit
harness changes and should be more robust across build systems.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133664 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22 23:23:19 +00:00
Francois Pichet
a7b1d170c6 Unbreak the CMake build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133574 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21 23:19:23 +00:00
Jim Grosbach
0b6a44afb9 Consolidate some TableGen diagnostic helper functions.
TableGen had diagnostic printers sprinkled about in a few places. Pull them
together into a single location in Error.cpp.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133568 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21 22:55:50 +00:00
Jakob Stoklund Olesen
9b718e8864 Skip fields that don't exist in the Register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133470 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-20 20:56:05 +00:00
Jakob Stoklund Olesen
4ce25d5d69 Add a RegisterTuples class to Target.td and TableGen.
A RegisterTuples instance is used to synthesize super-registers by
zipping together lists of sub-registers. This is useful for generating
pseudo-registers representing register sequence constraints like 'two
consecutive GPRs', or 'an even-odd pair of floating point registers'.

The RegisterTuples def can be used in register set operations when
building register classes. That is the only way of accessing the
synthesized super-registers.

For example, the ARM QQ register class of pseudo-registers could have
been formed like this:

  // Form pairs Q0_Q1, Q2_Q3, ...
  def QQPairs : RegisterTuples<[qsub_0, qsub_1],
                               [(decimate QPR, 2),
                                (decimate (shl QPR, 1), 2)]>;

  def QQ : RegisterClass<..., (add QQPairs)>;

Similarly, pseudo-registers representing '3 consecutive D-regs with
wraparound' look like:

  // Form D0_D1_D2, D1_D2_D3, ..., D30_D31_D0, D31_D0_D1.
  def DSeqTriples : RegisterTuples<[dsub_0, dsub_1, dsub_2],
                                   [(rotl DPR, 0),
                                    (rotl DPR, 1),
                                    (rotl DPR, 2)]>;

TableGen automatically computes aliasing information for the synthesized
registers.

Register tuples are still somewhat experimental. We still need to see
how they interact with MC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-20 02:50:54 +00:00
Chris Lattner
b2318662b6 fix the varargs version of StructType::get to not require an LLVMContext, making usage
much cleaner.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133364 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18 22:48:56 +00:00
Jakob Stoklund Olesen
c6596e2edc Use the correct comparator to avoid depending on pointer values.
This should fix the Linux buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133334 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18 05:44:55 +00:00
Jakob Stoklund Olesen
abdbc84b4e Store CodeGenRegisters as pointers so they won't be reallocated.
Reuse the CodeGenRegBank DenseMap in a few places that would build their
own or use linear search.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133333 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18 04:26:06 +00:00
Jakob Stoklund Olesen
54c47c1ce9 Remove MethodProtos/MethodBodies and allocation_order_begin/end.
Targets that need to change the default allocation order should use the
AltOrders mechanism instead. See the X86 and ARM targets for examples.

The allocation_order_begin() and allocation_order_end() methods have been
replaced with getRawAllocationOrder(), and there is further support
functions in RegisterClassInfo.

It is no longer possible to insert arbitrary code into generated
register classes. This is a feature.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133332 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18 03:08:20 +00:00
Jakob Stoklund Olesen
b4c704877d Provide AltOrders for specifying alternative allocation orders.
A register class can define AltOrders and AltOrderSelect instead of
defining method protos and bodies. The AltOrders lists can be defined
with set operations, and TableGen can verify that the alternative
allocation orders only contain valid registers.

This is currently an opt-in feature, and it is still possible to
override allocation_order_begin/end. That will not be true for long.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18 00:50:49 +00:00
Owen Anderson
23b0766b47 Fix formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133164 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16 16:52:24 +00:00
Jakob Stoklund Olesen
2559011a01 Prempt some obnoxious compiler from complaing about signed/unsigned
compares.

2^30 is actually the limit on the number of physical registers per
TargetRegisterInfo.h.

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2011-06-16 03:07:40 +00:00
Jakob Stoklund Olesen
0cc0929efc Make sure to pass an unsigned to a printf format that is always %u.
This should unbreak the native ARM testers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133141 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16 02:55:56 +00:00
Andrew Trick
05c087d893 Add support to lit for build mode requirements. e.g.
REQUIRES: Asserts
REQUIRES: Debug

This required chaining test configuration properties. It seems like a
generally good thing to do.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133131 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16 01:33:35 +00:00
Owen Anderson
77b4b13c2a Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 23:35:18 +00:00
John McCall
f14bacc862 Update the Clang diagnostic emitter to emit IDs for diagnostic categories.
Patch by Argyrios Kyrtzidis.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133093 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 21:43:52 +00:00
John McCall
3a3465b71d Add a new function attribute, nonlazybind, which inhibits lazy-loading
optimizations when emitting calls to the function;  instead those calls may
use faster relocations which require the function to be immediately resolved
upon loading the dynamic object featuring the call.  This is useful when it
is known that the function will be called frequently and pervasively and
therefore there is no merit in delaying binding of the function.

Currently only implemented for x86-64, where it turns into a call through
the global offset table.

Patch by Dan Gohman, who assures me that he's going to add LangRef documentation
for this once it's committed.



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2011-06-15 20:36:13 +00:00
Owen Anderson
1e56a2a85f Replace the statically generated hashtables for checking register relationships with just scanning the (typically tiny) static lists.
At the time I wrote this code (circa 2007), TargetRegisterInfo was using a std::set to perform these queries.  Switching to the static hashtables was an obvious improvement, but in reality there's no reason to do anything other than scan.
With this change, total LLC time on a whole-program 403.gcc is reduced by approximately 1.5%, almost all of which comes from a 15% reduction in LiveVariables time.  It also reduces the binary size of LLC by 86KB, thanks to eliminating a bunch of very large static tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133051 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 06:53:50 +00:00
Jakob Stoklund Olesen
59f26aadce Use a SetTheory instance to expand register lists in register classes.
This prepares tablegen to compute register lists from set theoretic dag
expressions. This doesn't really make any difference as long as
Target.td still declares RegisterClass::MemberList as [Register].

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133043 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 05:09:20 +00:00
Jakob Stoklund Olesen
ae1920b1ef Give CodeGenRegisterClass a real sorted member set.
Make the Elements vector private and expose an ArrayRef through
getOrder() instead. getOrder will eventually provide multiple
user-specified allocation orders.

Use the sorted member set for member and subclass tests. Clean up a lot
of ad hoc searches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133040 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 04:50:36 +00:00
Bill Wendling
393c4047c0 Improve the heuristic to emit the alias if the number of hard-coded registers
are also greater than the alias.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 04:31:19 +00:00
Jakob Stoklund Olesen
7b9cafde5e Move the list of register classes into CodeGenRegBank as well.
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133029 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 00:20:40 +00:00
Jakob Stoklund Olesen
952036def9 Fix a compile time regression caused by too small hash tables.
Measure the worst case number of probes for a miss instead of the less
conservative number of probes required for an insertion.

Lower the limit to < 6 probes worst case.

This doubles the size of the ARM and X86 hash tables, other targets are
unaffected. LiveVariables runs 12% faster with this change.

<rdar://problem/9598545>

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2011-06-14 16:58:16 +00:00
Bill Wendling
740e5b3586 Heuristic: If the number of operands in the alias are more than the number of
operands in the aliasee, don't print the alias.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132963 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14 03:17:20 +00:00
Jakob Stoklund Olesen
b95fd2d5fd Tweak hash function and compress hash tables.
Make the hash tables as small as possible while ensuring that all
lookups can be done in less than 8 probes.

Cut the aliases hash table in half by only storing a < b pairs - it
is a symmetric relation.

Use larger multipliers on the initial hash function to ensure that it
properly covers the whole table, and to resolve some clustering in the
very regular ARM register bank.

This reduces the size of most of these tables by 4x - 8x. For instance,
the ARM tables shrink from 48 KB to 8 KB.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-12 07:04:32 +00:00
Jakob Stoklund Olesen
bf710cc23e Remove now dead code.
These computations have been moved to CodeGenRegisters.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132887 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-12 07:04:28 +00:00
Jakob Stoklund Olesen
4091b059ec Extract the generateHashTable function.
The constant hash tables for sub-registers and overlaps are generated
the same way, so extract a function to generate and print the hash
table.

Also use the information computed by CodeGenRegisters.cpp instead of the
locally data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132886 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-12 07:04:26 +00:00
Jakob Stoklund Olesen
026dc223ae Compute lists of sub-regs, super-regs, and overlapping regs.
Besides moving structural computations to CodeGenRegisters.cpp, this
also well-defines the order of these lists:

- Sub-register lists come from a pre-order traversal of the graph
  defined by the SubRegs lists in the .td files.

- Super-register lists are topologically ordered so no register comes
  before any of its sub-registers. When the sub-register graph is not a
  tree, independent super-registers appear in numerical order.

- Lists of overlapping registers are ordered according to register
  number.

This reverses the order of the super-regs lists, but nobody was
depending on that. The previous order of the overlaps lists was odd, and
it may have depended on the precise behavior of std::stable_sort.

The old computations are still there, but will be removed shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132881 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-12 03:05:52 +00:00
Jakob Stoklund Olesen
b5923db192 Move the list of registers into CodeGenRegBank.
Also move the sub-register index computations from RegisterInfoEmitter
into CodeGenRegBank.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132865 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-11 00:28:06 +00:00
Jakob Stoklund Olesen
dc29c44713 Move some sub-register index calculations to CodeGenRegisters.cpp
Create a new CodeGenRegBank class that will eventually hold all the code
that computes the register structure from Records.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132849 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-10 18:40:00 +00:00
Jakob Stoklund Olesen
f1e2b23dfa Move TableGen's register bank classes to their own source file.
I'll be moving some more code there to gather all of the
register-specific stuff in one place. Currently it is shared between
CodeGenTarget and RegisterInfoEmitter.

The plan is that CodeGenRegisters can compute the full register bank
structure while RegisterInfoEmitter only will handle the printing part.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132788 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09 18:42:07 +00:00
Bob Wilson
e450a0046b Add special-case range checking for VCVT_N intrinsic immediate operands.
Radar 9558930.

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2011-06-09 16:57:29 +00:00
Chad Rosier
36a300ac02 Fixed a few illegal paths with llvm_unreachable. Patch by Cameron McInally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132732 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07 20:41:31 +00:00
Jakob Stoklund Olesen
c017bc1c1e Drop a RecordKeeper reference that wasn't necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-04 07:49:55 +00:00
Jakob Stoklund Olesen
1023f5a42d Silence compiler warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132624 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-04 05:09:36 +00:00
Jakob Stoklund Olesen
1de99829b6 Teach TableGen to evaluate DAG expressions as set operations.
A TableGen backend can define how certain classes can be expanded into
ordered sets of defs, typically by evaluating a specific field in the
record. The SetTheory class can then evaluate DAG expressions that refer
to these named sets.

A number of standard set and list operations are predefined, and the
backend can add more specialized operators if needed. The -print-sets
backend is used by SetTheory.td to provide examples.

This is intended to simplify how register classes are defined:

  def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>;

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132621 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-04 04:11:37 +00:00
Nick Lewycky
b2afe8759d Rework the logic to not rely on undefined behaviour (1LL << 64). Also simplify.
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2011-06-03 08:25:39 +00:00
Jakob Stoklund Olesen
f462e3fac7 Make it possible to have unallocatable register classes.
Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
register classes were given an empty allocation order, but now you can
say 'let isAllocatable=0' in the register class definition.

TableGen calculates if a register is part of any allocatable register
class, and makes that information available in TargetRegisterDesc::inAllocatableClass.

The goal here is to eliminate use cases for overriding allocation_order_*
methods.

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2011-06-02 23:07:20 +00:00
Joerg Sonnenberger
dd137903e4 Add new -d option to tblgen. It writes a make(1)-style dependency file.
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2011-06-01 13:10:15 +00:00
Bruno Cardoso Lopes
895c1e2dee Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value
must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.

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2011-05-31 03:33:27 +00:00
Rafael Espindola
6e032942cf Use the dwarf->llvm mapping to print register names in the cfi
directives.

Fixes PR9826.

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2011-05-30 20:20:15 +00:00
Rafael Espindola
7a067cc6e0 Introduce the DwarfRegAlias class for declaring that two registers have the
same dwarf number. This will be used for creating a dwarf number to register
mapping.

The only case that needs this so far is the XMM/YMM registers that unfortunately
do have the same numbers.

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2011-05-30 17:49:59 +00:00
John McCall
bd0fa4c00d Change how tblgen generates attributes for intrinsics to use a single
switch.  With this newfound organization, teach tblgen how not to give
all intrinsics the 'nounwind' attribute.  Introduce a new intrinsic,
llvm.eh.resume, which does not have this attribute.  Documentation and uses
to follow.



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2011-05-28 06:31:34 +00:00
Rafael Espindola
7bf114c1bd Fix the root cause of the bootstrap failure:
There was no way to check if a given register/mode pair was valid. We now return
an error code (-2) instead of asserting. If anyone thinks that an assert
at this point  is really needed, we can autogen a hasValidDwarfRegNum instead.

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2011-05-28 00:13:01 +00:00
Argyrios Kyrtzidis
804cb23305 [tablegen] A couple of changes to ClangDiagnosticEmmitter.
-Emit an empty warning option as string ("") instead of 0.
-For diagnostic names also emit the size of the string.


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2011-05-25 05:04:22 +00:00
Bill Wendling
f415d8b646 Use a more efficient data structure for the "operand map". The number of
operands to an instruction aren't great, so an iterative search is fairly quick
and doesn't have the overhead of std::map.


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2011-05-23 00:18:33 +00:00
Cameron Zwarich
3a2d255ce6 Fix PR9947 by placing OPFL_MemRefs on the node using memory operands rather than
the root if there is only one such node. This leaves only 2 verifier failures in
the entire test suite when running "make check".

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2011-05-19 21:13:30 +00:00
Tanya Lattner
2a8eb722c7 In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32.
Updated test case and reverted change to the PerfectShuffle Table.


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2011-05-18 06:42:21 +00:00
Tanya Lattner
c81c9709ef vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case.
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2011-05-17 20:48:40 +00:00
Jakob Stoklund Olesen
4bfc6fba78 Downgrade a tablegen warning to an error.
Ambiguous sub-register index compositions are OK as long as the backend writer
knows what he is doing.

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2011-05-10 17:52:59 +00:00
Mon P Wang
183c627d89 Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32
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2011-05-09 17:47:27 +00:00
Jakob Stoklund Olesen
123cab9480 Teach TableGen to automatically generate missing SubRegIndex instances.
The RegisterInfo.td file should only specify the indexes that sources need to
refer to. The rest is inferred.

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2011-05-07 21:22:39 +00:00
Jim Grosbach
5d754bfa32 Improve diagnostics for some parse errors. Not asserting when a user input
error is detected is a good thing.

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2011-05-06 18:47:45 +00:00
Jim Grosbach
96883ec700 ParseFile() may throw, so extend the try/catch to handle that.
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2011-05-06 18:39:28 +00:00
Mikhail Glushenkov
3a21c55a14 llvmc: Make it possible to provide an argument to (join).
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2011-05-05 04:24:58 +00:00
Nick Lewycky
9f1569a3f7 The system suppression file should catch these, but since they *once again* are
not, I'll just add them here and be done with it.


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2011-05-04 01:03:02 +00:00
Jim Grosbach
b9d5af05fd Tidy up. Add missing newline to generated file.
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2011-05-03 19:09:56 +00:00
Eli Friedman
206a10cf28 Filter out pattterns from the FastISel emitter which it doesn't actually know how to handle. No significant functionality change at the moment, but it's necessary for some changes I'm planning.
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2011-04-29 21:58:31 +00:00
Nick Lewycky
bcffb1fbb8 Rename profile_rt.so to libprofile_rt.so under configure+make (it already was
under cmake).

Add libprofile_rt.a so that we can tell clang to link against it in --coverage
mode. Also turn it on by default in cmake builds.

Oscar, this touches a change you made for EXCLUDE_FROM_ALL support -- I think
I've done the right thing, but please let me know (or fix and commit) if not!


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2011-04-29 02:12:06 +00:00
Owen Anderson
4cdcb4772d Fix a bug in tblgen that caused incorrect encodings on instructions that specified operands with "bit" instead of "bits<1>".
Unfortunately, my only testcase for this is fragile, and the ARM AsmParser can't round trip the instruction in question.
<rdar://problem/9345702>


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2011-04-28 17:51:45 +00:00
Mikhail Glushenkov
4e699cf518 Add a TODO.
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2011-04-24 14:17:41 +00:00
Jay Foad
ddcdcc8863 Remove unused STL header includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130068 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-23 19:53:52 +00:00
Johnny Chen
597fa65373 Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should
print out ldr, not ldr.n.

rdar://problem/9267772


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2011-04-22 19:12:43 +00:00
Bob Wilson
c1fe100f35 Define Neon load/store intrinsics for Clang as macros instead of functions.
This is needed so the front-end can see "aligned" attributes on the type
for the pointer arguments.  Radar 9311427.

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2011-04-22 00:37:01 +00:00
Jakob Stoklund Olesen
69ba413057 Don't allow per-register spill size and alignment.
These values were not used for anything. Spill size and alignment is a property
of the register class, not the register.

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2011-04-21 03:43:21 +00:00
Jakob Stoklund Olesen
6bfba2e5af Prefer cheap registers for busy live ranges.
On the x86-64 and thumb2 targets, some registers are more expensive to encode
than others in the same register class.

Add a CostPerUse field to the TableGen register description, and make it
available from TRI->getCostPerUse. This represents the cost of a REX prefix or a
32-bit instruction encoding required by choosing a high register.

Teach the greedy register allocator to prefer cheap registers for busy live
ranges (as indicated by spill weight).

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2011-04-20 18:19:48 +00:00