Evan Cheng
fa5a91a71e
Undo 48570. Correctly match mmx shift instructions with an immediate operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48627 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-21 00:40:09 +00:00
Chris Lattner
f70107fe1c
add a note.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48583 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-20 04:46:13 +00:00
Evan Cheng
260e07ec8c
Fix this xform: (sra (shl X, m), result_size) -> (sign_extend (trunc (shl X, result_size - n - m)))
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48578 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-20 02:18:41 +00:00
Chris Lattner
71a2cb25eb
detabify llvm, patch by Mike Stump!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48577 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-20 01:22:40 +00:00
Scott Michel
79698f60c4
Add more patterns to match in the integer comparison test harnesses.
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Fix bugs encountered, mostly due to range matching for immediates;
the CellSPU's 10-bit immediates are sign extended, covering a
larger range of unsigned values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48575 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-20 00:51:36 +00:00
Evan Cheng
dff1dcac6c
Add intrinsics to match mmx shift builtin's with immediate operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48569 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-19 23:38:52 +00:00
Devang Patel
c758209153
PassInfo keep tracks whether a pass is an analysis pass or not.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48554 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-19 21:56:59 +00:00
Dan Gohman
7925ed05d0
Add support for multiple return values for the PPC target by
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converting call result lowering to use the CallingConvLowering
infastructure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48552 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-19 21:39:28 +00:00
Arnold Schwaighofer
4fe3073cfb
Don't loose incoming argument registers. Fix documentation style.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48545 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-19 16:39:45 +00:00
Christopher Lamb
15cbde3cf6
Fix X86's isTruncateFree to not claim that truncate to i1 is free. This fixes Bill's testcase that failed for r48491.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48542 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-19 08:30:06 +00:00
Bill Wendling
bebc3642d3
On Darwin, GCC issues a ".globl" for something that has a "visibility protected"
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attribute instead of ".protected".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48516 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-18 23:38:12 +00:00
Evan Cheng
586ccac4ec
Fix a x86-64 isel lowering bug that's been around forever. A x86-64 varargs function implicitly reads X86::AL, don't clobber it!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48515 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-18 23:36:35 +00:00
Dale Johannesen
257f75d0b8
Make Complex long long/double/long double work
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in ppc64 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48459 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-17 17:11:08 +00:00
Chris Lattner
315123fb6a
Check in some #ifdef'd out code switching call argument
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lowering over to SparcCallingConv.td. We can't make the switch
yet because we can't say to pass f64 registers in 2 x i32 registers
with the td file yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48449 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-17 06:58:37 +00:00
Chris Lattner
e0b1215a92
minor cleanups
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48448 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-17 06:57:02 +00:00
Evan Cheng
d183307639
Unbreak JIT. Ignore TargetInstrInfo::IMPLICIT_DEF.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48447 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-17 06:56:52 +00:00
Chris Lattner
b26bc75213
remove dead code
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48445 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-17 06:04:10 +00:00
Chris Lattner
98949a6d2c
Switch sparc from using LowerCallTo to using LowerOperation(CALL) like
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other targets. Use autogenerated calling conv to lower result of
calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48444 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-17 06:01:07 +00:00
Chris Lattner
5a65b92830
Start moving sparc to use SparcCallingConv.td, switching over
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return lowering first. This fixes a bug where the top and bottom
of i64 values were returned in the wrong registers before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48443 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-17 05:41:48 +00:00
Chris Lattner
d23405e6f0
split sparc lowering out into SparcISelLowering.{cpp|h} to follow
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best practices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48442 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-17 03:21:36 +00:00
Chris Lattner
601fe38b1e
refactor the LowerOperation code out to individual functions for
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each lowering, which is 'best practice'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48441 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-17 02:52:07 +00:00
Dale Johannesen
fdd3ade005
Next round of PPC32 ABI changes. Allow for gcc
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behavior where a callee thinks a param will be
present in memory, even though the ABI doc says
it doesn't have to be. Handle complex long long
and complex double (4 and 8 return regs).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48439 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-17 02:13:43 +00:00
Chris Lattner
349155b671
various rotate fun.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48438 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-17 01:47:51 +00:00
Nate Begeman
bc4efb8ac7
Add a couple missing SSE4 instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48430 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-16 21:14:46 +00:00
Gordon Henriksen
3e0c835593
C and Objective Caml bindings for the TargetData class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48422 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-16 20:08:03 +00:00
Christopher Lamb
c929823525
Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48412 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-16 03:12:01 +00:00
Evan Cheng
20ccded7de
Remove isImplicitDef TargetInstrDesc flag.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48381 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-15 00:19:36 +00:00
Evan Cheng
da47e6e0d0
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-15 00:03:38 +00:00
Dale Johannesen
8f5422c24b
Implement the real calling convention for ppc32 Altivec:
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vectors go at the end of the memory area, after all
non-vector parameters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48364 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-14 17:41:26 +00:00
Evan Cheng
029d9dafa0
Fix some 80 col violations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48361 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-14 07:46:48 +00:00
Evan Cheng
172b794cd5
Fix a number of encoding bugs. SSE 4.1 instructions MPSADBWrri, PINSRDrr, etc. have 8-bits immediate field (ImmT == Imm8).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48360 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-14 07:39:27 +00:00
Evan Cheng
17ed8fa63d
Add debugging stuff.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48359 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-14 07:13:42 +00:00
Chris Lattner
69a74ab421
Add an issue that is preventing instcombine from doing a simplification.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48356 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-14 06:00:19 +00:00
Dan Gohman
704df9fcbd
Use SDTNone instead of duplicating it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48346 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-13 23:07:40 +00:00
Christopher Lamb
6634e26aa1
Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects.
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Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48329 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-13 05:47:01 +00:00
Dale Johannesen
d75686a471
Do not promote float params to double in varargs
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calls here. This was done earlier for params in
the varargs part of the params; any float params
that survive to here are in the non-varargs part,
and must not be promoted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48310 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 23:40:01 +00:00
Chris Lattner
58d74910c6
Reimplement the parameter attributes support, phase #1 . hilights:
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1. There is now a "PAListPtr" class, which is a smart pointer around
the underlying uniqued parameter attribute list object, and manages
its refcount. It is now impossible to mess up the refcount.
2. PAListPtr is now the main interface to the underlying object, and
the underlying object is now completely opaque.
3. Implementation details like SmallVector and FoldingSet are now no
longer part of the interface.
4. You can create a PAListPtr with an arbitrary sequence of
ParamAttrsWithIndex's, no need to make a SmallVector of a specific
size (you can just use an array or scalar or vector if you wish).
5. All the client code that had to check for a null pointer before
dereferencing the pointer is simplified to just access the
PAListPtr directly.
6. The interfaces for adding attrs to a list and removing them is a
bit simpler.
Phase #2 will rename some stuff (e.g. PAListPtr) and do other less
invasive changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48289 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 17:45:29 +00:00
Evan Cheng
c8e3b147ee
Clean up my own mess.
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X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48279 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 07:02:50 +00:00
Dale Johannesen
404d99010d
One more bit of Altivec parameter passing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48269 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 00:49:20 +00:00
Dale Johannesen
75092de483
Implement Altivec passing to varargs functions on ppc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48264 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-12 00:22:17 +00:00
Anton Korobeynikov
4d86e2a6b8
Correctly propagate thread-local flag from aliasee to alias. This fixes PR2137
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48257 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11 22:38:53 +00:00
Dan Gohman
bfae83139d
Use PassManagerBase instead of FunctionPassManager for functions
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that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48256 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11 22:29:46 +00:00
Chris Lattner
e12ecf272d
Implement basic support for the 'f' register class constraint. This basically
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works, but probably won't if you mix it with 't' or 'u' yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48243 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11 19:50:13 +00:00
Chris Lattner
1d38677e34
coalesce away 80-bit floating point copies.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48241 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11 19:30:09 +00:00
Chris Lattner
07f7cc3ddb
convert a massive if statement to a switch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48240 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11 19:28:17 +00:00
Chris Lattner
fce84acbbc
start handling the 'f' x87 constraint.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48239 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11 19:06:29 +00:00
Christopher Lamb
1bc1008b38
Missed part of recommit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48224 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11 10:27:36 +00:00
Christopher Lamb
1fab4a6bbb
Recommitting parts of r48130. These do not appear to cause the observed failures.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48223 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11 10:09:17 +00:00
Evan Cheng
fa2f786f4e
If there are multiple register classes that a register belongs to, return the super-class (e.g. on x86, returns GR32, not GR32_).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48220 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11 07:54:14 +00:00
Evan Cheng
676dd7c80b
When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48218 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11 07:19:34 +00:00
Evan Cheng
204496d58e
In 32-bit mode, mark 64-bit GPR's as unallocatable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48217 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11 07:16:00 +00:00
Nick Lewycky
3c78697a3c
Fix the build on gcc 4.2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48212 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11 05:56:09 +00:00
Chris Lattner
447ff68c08
Change the model for FP Stack return to use fp operands on the
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RET instruction instead of using FpSET_ST0_32. This also generalizes
the code to handling returning of multiple FP results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48209 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11 03:23:40 +00:00
Dan Gohman
034f60ed24
Generalize ExpandIntToFP to handle the case where the operand is legal
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and it's the result that requires expansion. This code is a little confusing
because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type
(the integer type) rather than the result type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48206 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-11 01:59:03 +00:00
Chris Lattner
183275a627
abort with an assert instead of a cerr to get line#
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48199 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 23:56:08 +00:00
Scott Michel
405fba12ce
- Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency.
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- Add test pattern matching in CellSPU's icmp32.ll test harness
- Fix CellSPU fcmp.ll-generated assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48197 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 23:49:09 +00:00
Chris Lattner
03fdec04d1
Don't emit FP_REG_KILL into a block that just returns. Nothing
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can be live out of the block anyway, so it isn't needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48192 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 23:34:12 +00:00
Dale Johannesen
82e4289fc7
Disable prolog code that aligns the stack when a
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local object of >16 byte alignment exists. It does not
work and getting it to work is not trivial, as explained
in the comment. This fixes all the remaining ppc32
failures in the struct-layout-1 part of the gcc testsuite.
(gcc does not support this either, and the only way to
get such an object is with __attribute__((aligned)) or
generic vectors; it can't be done in a standard-conforming
program, or with Altivec. So I think disabling it is OK.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48188 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 22:59:46 +00:00
Bill Wendling
4a66e9a57e
Change the "enable/disable" mechanism so that we can enable PPC register
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scavenging for 32-bit and 64-bit separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48186 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 22:49:16 +00:00
Chris Lattner
8e6da15e54
Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to
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copyfromreg/copytoreg instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48174 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 21:08:41 +00:00
Evan Cheng
d2cde68855
Default ISD::PREFETCH to expand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48169 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 19:38:10 +00:00
Evan Cheng
4499e495ea
Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48167 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 19:31:26 +00:00
Chris Lattner
cb341de0e2
fix 80 col violations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48166 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 18:55:53 +00:00
Nicolas Geoffray
9348c69dcf
Stylistic modifications. No functionality changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48158 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 17:46:45 +00:00
Scott Michel
78c47fa50b
Integer comparison tests for CellSPU.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48152 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 16:58:52 +00:00
Scott Michel
5b8f82e35b
Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's
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return ValueType can depend its operands' ValueType.
This is a cosmetic change, no functionality impacted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48145 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 15:42:14 +00:00
Nicolas Geoffray
0404cd97e4
Add description of individual bits in CR. This fix PR1765.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48143 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 14:12:10 +00:00
Christopher Lamb
3feb0170a8
Allow insert_subreg into implicit, target-specific values.
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Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48130 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 06:12:08 +00:00
Dale Johannesen
b8cafe3427
Increase ISD::ParamFlags to 64 bits. Increase the ByValSize
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field to 32 bits, thus enabling correct handling of ByVal
structs bigger than 0x1ffff. Abstract interface a bit.
Fixes gcc.c-torture/execute/pr23135.c and
gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing
on ppc32, quietly producing wrong code on x86-32.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48122 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-10 02:17:22 +00:00
Chris Lattner
dc9971a2e3
Darwin PPC64 indirect call target goes in X12, not R12. This fixes these
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two regression tests:
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll
test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48120 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09 20:49:33 +00:00
Chris Lattner
5e09da236e
cell really does support cross-regclass moves, because R3 is in lots of different regclasses, and the code is not consistent when it comes to value tracking.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48119 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09 20:31:11 +00:00
Chris Lattner
68a0d0984d
make sure ar.pfs is in a register class, this fixes test/CodeGen/IA64/ret-0.ll
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48118 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09 20:12:44 +00:00
Chris Lattner
f30e1cf9b7
teach X86InstrInfo::copyRegToReg how to copy into ST(0) from
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an RFP register class.
Teach ScheduleDAG how to handle CopyToReg with different src/dst
reg classes.
This allows us to compile trivial inline asms that expect stuff
on the top of x87-fp stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48107 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09 09:15:31 +00:00
Chris Lattner
5c927500c8
add some code to support cross-register class copying from
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RST -> RFP{32/64/80}. We only handle ST(0) for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48104 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09 08:46:19 +00:00
Chris Lattner
90b347dc90
rearrange some code, no functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48101 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09 07:58:04 +00:00
Chris Lattner
8dc023f684
claim ST(x) registers are 80 bits, which is true. This doesn't affect
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codegen yet because these can't be spilled (they don't exist until after RA).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48098 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09 07:49:01 +00:00
Chris Lattner
afb23f48a4
rename FP_SETRESULT -> FP_SET_ST0
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48094 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09 07:08:44 +00:00
Chris Lattner
6fa2f9c636
rename FpGETRESULT32 -> FpGET_ST0_32 etc. Add support for
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isel'ing value preserving FP roundings from one fp stack reg to another
into a noop, instead of stack traffic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48093 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09 07:05:32 +00:00
Chris Lattner
67f453aae7
Finish implementing a readme entry: when inserting an i64 variable
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into a vector of zeros or undef, and when the top part is obviously
zero, we can just use movd + shuffle. This allows us to compile
vec_set-B.ll into:
_test3:
movl $1234567, %eax
andl 4(%esp), %eax
movd %eax, %xmm0
ret
instead of:
_test3:
subl $28, %esp
movl $1234567, %eax
andl 32(%esp), %eax
movl %eax, (%esp)
movl $0, 4(%esp)
movq (%esp), %xmm0
addl $28, %esp
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48090 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09 05:42:06 +00:00
Chris Lattner
f68cbceb17
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48064 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09 01:08:22 +00:00
Chris Lattner
62098040a1
Implement a readme entry, compiling
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#include <xmmintrin.h>
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}
into:
movl $1, %eax
movd %eax, %xmm0
ret
instead of a constant pool load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48063 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-09 01:05:04 +00:00
Chris Lattner
19f7969f81
1) Improve comments.
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2) Don't try to insert an i64 value into the low part of a
vector with movq on an x86-32 target. This allows us to
compile:
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}
into:
_doload64:
movaps LCPI1_0, %xmm0
ret
instead of:
_doload64:
subl $28, %esp
movl $0, 4(%esp)
movl $1, (%esp)
movq (%esp), %xmm0
addl $28, %esp
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48057 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-08 22:59:52 +00:00
Chris Lattner
c9517fb6eb
minor simplifications to this code, don't create a dead
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SCALAR_TO_VECTOR on paths that end up not using it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48056 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-08 22:48:29 +00:00
Chris Lattner
b607f9c822
This one looks easy, add a note.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48055 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-08 22:32:39 +00:00
Chris Lattner
f658ad10f6
move these to the appropriate file
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48054 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-08 22:28:45 +00:00
Dale Johannesen
7f96f3912e
More ppc32 byval handling (bug fixes). Things
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are looking pretty good now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48043 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-08 01:41:42 +00:00
Evan Cheng
27b7db549e
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48042 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-08 00:58:38 +00:00
Dan Gohman
a2fcff4d97
Add support for calls with i128 return values on ppc64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48041 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-08 00:19:12 +00:00
Bill Wendling
5f5bf3a3fd
PPC64 passes arguments of integral type in i64 registers, not i32. Reflect this
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by promoting smaller integral values (i32 at this point) to i64, then truncating
to get the wanted size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48030 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-07 20:49:02 +00:00
Dan Gohman
9ed06db5c8
Add support for lowering 128-bit shifts on ppc64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48029 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-07 20:36:53 +00:00
Dale Johannesen
8419dd6aa6
Next bits of PPC byval handling. Basically functional
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but there are bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48028 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-07 20:27:40 +00:00
Chris Lattner
af8ee84fe5
Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48027 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-07 20:18:24 +00:00
Chris Lattner
49bd37d369
Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to work
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with 32 or 64-bit operands/results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48026 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-07 20:13:51 +00:00
Chris Lattner
d1108222fd
mark frem as expand for all legal fp types on x86, regardless of whether
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we're using SSE or not. This fixes PR2122.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48006 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-07 06:36:32 +00:00
Gabor Greif
2cf36e0772
some more spelling changes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47996 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-06 10:51:21 +00:00
Scott Michel
4cb8bd8eff
Refine Cell's i64 constant generation code to cover more constants where the
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upper and lower 32-bits are the same (in addition to 0 and -1 previously.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47985 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-06 04:02:54 +00:00
Andrew Lenharth
6ad150baac
gcc likes things spelled correctly
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47981 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-05 23:41:37 +00:00
Dale Johannesen
1f797a32fd
Next bit of PPC ByVal handling; call-site code seems
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correct now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47978 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-05 23:31:27 +00:00
Scott Michel
ad2715e0d7
- Fix support for "special" i64 immediates that can be loaded
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using IL, ILA, et. al. v2i64 and i64 are now supported by
the select bits (SELB) instruction.
- Add missing comparison operations (testcase forthcoming)
- More multiclass refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47973 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-05 23:02:02 +00:00
Chris Lattner
4d93b2f16d
evan implemented this.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47948 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-05 17:11:51 +00:00