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Author SHA1 Message Date
Johnny Chen
6c3891067b Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. Modify the disassembler to handle that. 
rdar://problem/9184053


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128285 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 17:31:16 +00:00
Jakob Stoklund Olesen
15a3ea0628 Emit less labels for debug info and stop emitting .loc directives for DBG_VALUEs. 
The .dot directives don't need labels, that is a leftover from when we created
line number info manually.

Instructions following a DBG_VALUE can share its label since the DBG_VALUE
doesn't produce any code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128284 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 17:20:59 +00:00
Johnny Chen
f14d5cf33a Also need to handle invalid imod values for CPS2p. 
rdar://problem/9186136


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128283 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 17:03:12 +00:00
Duncan Sands
067e2e2adb Useful script for finding regressions in the nightly testsuite. 
I think it was written by Pawel Worach.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128268 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 07:17:44 +00:00
Bill Wendling
1a59243c25 Remove redundant compression option. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128267 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 06:43:59 +00:00
Andrew Trick
336298cf2c Fix for -pre-RA-sched=source. 
Yet another case of unchecked NULL node (for physreg copy).
May fix PR9509.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128266 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 06:40:55 +00:00
Nick Lewycky
628b337561 No functionality change, just adjust some whitespace for coding style compliance. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128257 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 06:05:50 +00:00
Nick Lewycky
d56acb36ab No functionality change. Fix up some whitespace and switch out "" for '' when 
printing a single character.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128256 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 06:04:26 +00:00
Jakob Stoklund Olesen
eb5067e0d9 Ignore special ARM allocation hints for unexpected register classes. 
Add an assertion to linear scan to prevent it from allocating registers outside
the register class.

<rdar://problem/9183021>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128254 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 01:48:18 +00:00
Johnny Chen
a7078c4f27 Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed), 
modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128252 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 01:09:48 +00:00
Johnny Chen
ef74e9ab40 delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 instructions, and add a test case for that. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128249 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-25 00:17:42 +00:00
Johnny Chen
8c13335c9a The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been stale since 
the change to ("tLDMIA", "tLDMIA_UPD").  Update the conflict resolution code and add
test cases for that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128247 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 23:42:31 +00:00
Johnny Chen
1090d7711b The ARM disassembler was confused with the 16-bit tSTMIA instruction. 
According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available.
Ignore tSTMIA for the decoder emitter and add a test case for that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128246 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 23:21:14 +00:00
Devang Patel
439e0c79f5 Move test in x86 specific area. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128245 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 22:39:09 +00:00
Matt Beaumont-Gay
1866af4a98 Suppress an unused variable warning in -asserts builds 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128244 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 22:05:48 +00:00
Johnny Chen
c39b6271be Handle the added VBICiv*i* NEON instructions, too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128243 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 22:04:39 +00:00
Eric Christopher
18a41c92c3 Testcase for llvm-gcc commit r128230. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128242 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 21:59:03 +00:00
Johnny Chen
8cb988686d Plug a leak by ThumbDisassembler::getInstruction(), thanks to Benjamin Kramer! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128241 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 21:42:55 +00:00
Johnny Chen
9091bf25d9 T2 Load/Store Multiple: 
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128240 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 21:36:56 +00:00
Benjamin Kramer
83ccbff84f Plug a leak in the arm disassembler and put the tests back. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128238 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 21:14:28 +00:00
Bruno Cardoso Lopes
505f3cd296 Add asm parsing support w/ testcases for strex/ldrex family of instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 21:04:58 +00:00
Johnny Chen
02af767dca Remove these two test files as they cause llvm-i686-linux-vg_leak build to fail 'test-llvm'. 
These two are test cases which should result in 'invalid instruction encoding' from running llvm-mc -disassemble.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128235 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 20:56:23 +00:00
Johnny Chen
e6d69e7dbe ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled. 
Set the encoding bits to {0,?,?,0}, not 0.  Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128234 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 20:42:48 +00:00
Devang Patel
23670e5b95 Keep track of directory namd and fIx regression caused by Rafael's patch r119613. 
A better approach would be to move source id handling inside MC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128233 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 20:30:50 +00:00
Jim Grosbach
d31d304f83 Clean up assembly statement separator support. 
The MC asm lexer wasn't honoring a non-default (anything but ';') statement
separator. Fix that, and generalize a bit to support multi-character
statement separators.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128227 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 18:46:34 +00:00
Johnny Chen
b4ac342ea0 The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the 
VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function.  Add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128226 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 18:40:38 +00:00
Johnny Chen
ce1868b21c Add comments to the handling of opcode CPS3p to reject invalid instruction encoding, 
a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128220 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 17:04:22 +00:00
Andrew Trick
0a828fd7ef revert r128199 until it can be made to work with Frontend/dependency-gen.c. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128218 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 16:43:37 +00:00
Cameron Zwarich
9035484200 Debug intrinsics must be skipped at the beginning and ends of blocks, lest they 
affect the generated code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128217 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 16:34:59 +00:00
Jay Foad
0d4b81519d Fix typo in comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128216 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 16:18:19 +00:00
Chris Lattner
49e0ccfa78 fix description, PR9542 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128214 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 16:13:31 +00:00
Cameron Zwarich
dc31cfeb74 It is enough for the CallInst to have no uses to be made a tail call with a ret 
void; it doesn't need to have a void type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128212 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 15:54:11 +00:00
Devang Patel
52e37df8c0 s/UpdateDT/ModifiedDT/g 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128211 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 15:35:25 +00:00
NAKAMURA Takumi
a2e0762fae Target/X86: [PR8777][PR8778] Tweak alloca/chkstk for Windows targets. 
FIXME: Some cleanups would be needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128206 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 07:07:00 +00:00
NAKAMURA Takumi
c37c539944 llvm-stub.cpp: mingw-w64 tweak. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128205 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 07:06:45 +00:00
Evan Cheng
acdddfedd1 Add comment to clarify what MachineConstantPoolEntry::isMachineConstantPoolEntry() means. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128204 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 06:28:45 +00:00
Evan Cheng
d700617193 Nasty bug in ARMBaseInstrInfo::produceSameValue(). The MachineConstantPoolEntry 
entries being compared may not be ARMConstantPoolValue. Without checking
whether they are ARMConstantPoolValue first, and if the stars and moons
are aligned properly, the equality test may return true (when the first few
words of two Constants' values happen to be identical) and very bad things can
happen.

rdar://9125354


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128203 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 06:20:03 +00:00
Michael J. Spencer
e1db1b8d4e Remove all uses of PATH_MAX and MAXPATHLEN from PathV2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128199 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 05:23:40 +00:00
Cameron Zwarich
6e8ffc1c4d Do early taildup of ret in CodeGenPrepare for potential tail calls that have a 
void return type. This fixes PR9487.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128197 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 04:52:10 +00:00
Cameron Zwarich
4bae588c75 Use an early return instead of a long if block. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128196 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 04:52:07 +00:00
Cameron Zwarich
680c962ebd When UpdateDT is set, DT is invalid, which could cause problems when trying to 
use it later. I couldn't make a test that hits this with the current code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128195 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 04:52:04 +00:00
Cameron Zwarich
661a390b83 Check for TLI so that -codegenprepare can be used from opt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128194 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 04:51:51 +00:00
Johnny Chen
e4000595fb CPS3p: Let's reject impossible imod values by returning false from the DisassembleMiscFrm() function. 
Fixed rdar://problem/9179416 ARM disassembler crash: "Unknown imod operand" (fuzz testing)

Opcode=98 Name=CPS3p Format=ARM_FORMAT_MISCFRM(26)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

Before:
	cpsUnknown imod operand
UNREACHABLE executed at /Volumes/data/lldb/llvm/lib/Target/ARM/InstPrinter/../ARMBaseInfo.h:123!

After:
/Volumes/data/Radar/9179416/mc-input-arm.txt:1:1: warning: invalid instruction encoding
0x93 0x1c 0x2 0xf1
^


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128192 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 02:24:36 +00:00
Johnny Chen
3d793962be Load/Store Multiple: 
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add two test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128191 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 01:40:42 +00:00
Johnny Chen
571f290376 STRT and STRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821). 
We now tag them as IndexModePost.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 01:07:26 +00:00
Johnny Chen
2abc9d2444 The r128103 fix to cope with the removal of addressing modes from the MC instructions 
were incomplete.  The assert stmt needs to be updated and the operand index incrment is wrong.
Fix the bad logic and add some sanity checking to detect bad instruction encoding;
and add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128186 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-24 00:28:38 +00:00
Jim Grosbach
5ffe37f2c7 Runtime dylib simple ARM 24-bit branch relocation support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128184 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 23:35:17 +00:00
Devang Patel
36dca60f5c Enable GlobalMerge on darwin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128183 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 23:34:19 +00:00
Jim Grosbach
b9b1e307f2 Fix comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128182 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 23:32:48 +00:00
Andrew Trick
f6c39412dd Revert r128175. 
I'm backing this out for the second time. It was supposed to be fixed by r128164, but the mingw self-host must be defeating the fix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128181 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-23 23:11:02 +00:00