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1170 Commits

Author SHA1 Message Date
Owen Anderson
af399a6ffe XFAIL this test. It only worked before because of a bug in the spill point selection code. Not deleting because 
it should be possible to enhance the selection code to handle this in the future.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63340 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-29 22:27:56 +00:00
Evan Cheng
d5a4802708 Local register allocator shouldn't assume only the entry and landing pad basic blocks have live-ins. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63323 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-29 18:37:30 +00:00
Dan Gohman
197e88f796 In the case of an extractelement on an insertelement value, 
the element indices may be equal if either one is not a
constant.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63311 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-29 16:10:46 +00:00
Evan Cheng
5a3c6a87b0 Exit with nice warnings when register allocator run out of registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63267 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-29 02:20:59 +00:00
Dan Gohman
e5af2d3a22 Make x86's BT instruction matching more thorough, and add some 
dagcombines that help it match in several more cases. Add
several more cases to test/CodeGen/X86/bt.ll. This doesn't
yet include matching for BT with an immediate operand, it
just covers more register+register cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63266 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-29 01:59:02 +00:00
Mon P Wang
e91a000889 Fixed lowering of v816 shuffles. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63252 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-28 23:11:14 +00:00
Bill Wendling
7540561097 Make test platform agnostic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63247 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-28 22:20:56 +00:00
Evan Cheng
1632782fe9 The memory alignment requirement on some of the mov{h|l}p{d|s} patterns are 16-byte. That is overly strict. These instructions read / write f64 memory locations without alignment requirement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63195 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-28 08:35:02 +00:00
Mon P Wang
f4646d9902 Added sse test patterns for r62979 and r63193. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63194 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-28 08:13:56 +00:00
Bill Wendling
ac7de20a49 Add testcase for r63142. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63149 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-27 23:00:53 +00:00
Evan Cheng
6a86bd71df Implement multiple with overflow by 2 with an add instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63090 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-27 03:30:42 +00:00
Dan Gohman
4e1fae5125 Add a regression test for x86-64 red zone usage. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63075 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-27 00:40:27 +00:00
Duncan Sands
5bb11b89dd Fix PR3393, which amounts to a bug in the expensive 
checking logic.  Rather than make the checking more
complicated, I've tweaked some logic to make things
conform to how the checking thought things ought to
be, since this results in a simpler "mental model".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63048 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-26 21:54:18 +00:00
Dan Gohman
4699934647 At Nick Lewycky's request, rename this test with a more informative name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63042 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-26 21:36:31 +00:00
Evan Cheng
5b2e5893c6 Enhance logic in X86DAGToDAGISel::PreprocessForRMW which move load inside callseq_start to allow it to be folded into a call. It was not considering the cases where a token factor is between the load and the callseq_start. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63022 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-26 18:43:34 +00:00
Nate Begeman
51a0437b16 Map address space 256 to gs; similar mappings could be supported for the 
other x86 segments.  address space 0 is stack/default, 1-255 are reserved for
client use.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62980 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-26 01:24:32 +00:00
Torok Edwin
c8ad2d2abf revert this patch for now, because Codegen does still want to generate SSE code, 
for example in the case of va-args. XFAIL associated tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62972 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-25 20:21:24 +00:00
Torok Edwin
7f1d5252c7 If user explicitly asks not to use SSE, don't force it. This fixes LLVM part of PR3402. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62967 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-25 17:58:56 +00:00
Evan Cheng
d498c8f2c8 Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue. 
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1                                                                                                                                     
%reg1029<def> = MOV8rr %reg1028                                                                                                                                                      
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>                                                                                                                            
insert => %reg1030<def> = MOV8rr %reg1028                                                                                                                                            
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>                                                                                                         

In this case, it might not be possible to coalesce the second MOV8rr                                                                                                                 
instruction if the first one is coalesced. So it would be profitable to                                                                                                              
commute it:                                                                                                                                                                          
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1                                                                                                                                     
%reg1029<def> = MOV8rr %reg1028                                                                                                                                                      
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>                                                                                                                            
insert => %reg1030<def> = MOV8rr %reg1029                                                                                                                                            
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62954 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-25 03:53:59 +00:00
Dan Gohman
54e853a779 Add a PR comment to this test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62921 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-24 17:32:54 +00:00
Evan Cheng
3e2351fa2a Update test to reflect command line option name change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62836 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-23 05:45:31 +00:00
Dan Gohman
760f86f339 Don't create ISD::FNEG nodes after legalize if they aren't legal. 
Simplify x+0 to x in unsafe-fp-math mode. This avoids a bunch of
redundant work in many cases, because in unsafe-fp-math mode,
ISD::FADD with a constant is considered free to negate, so the
DAGCombiner often negates x+0 to -0-x thinking it's free, when
in reality the end result is -x, which is more expensive than x.

Also, combine x*0 to 0.

This fixes PR3374.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62789 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-22 21:58:43 +00:00
Devang Patel
5e3c013f81 Do not use buggy llvm-gcc to generate testcases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62770 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-22 18:28:11 +00:00
Bill Wendling
708f5a8fb6 Now with RUN line. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62716 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-21 21:28:03 +00:00
Bill Wendling
e3b014a05f Run this through -simplifycfg and -mem2reg to test only what we need to test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62714 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-21 21:02:27 +00:00
Dan Gohman
764fd0cbc8 Simplify ReduceLoadWidth's logic: it doesn't need several different 
special cases after producing the new reduced-width load, because the
new load already has the needed adjustments built into it. This fixes
several bugs due to the special cases, including PR3317.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62692 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-21 15:17:51 +00:00
Dan Gohman
1ef4d8f7ee Fix a recent regression. ClrOpcode is not set for i8; for i8, if 
we want to clear %ah to zero before a division, just use a
zero-extending mov to %al. This fixes PR3366.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62691 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-21 14:50:16 +00:00
Evan Cheng
aaf414c92c Favors generating "not" over "xor -1". For example. 
unsigned test(unsigned a) {
  return ~a;
}
llvm used to generate:
movl    $4294967295, %eax
xorl    4(%esp), %eax

Now it generates:
movl      4(%esp), %eax
notl      %eax

It's 3 bytes shorter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62661 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-21 02:09:05 +00:00
Owen Anderson
6cf7c390ec Be more aggressive about renumbering vregs after splitting them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62639 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-21 00:13:28 +00:00
Evan Cheng
a894ae130b Fix PR3243: a LiveVariables bug. When HandlePhysRegKill is checking whether the last reference is also the last def (i.e. dead def), it should also check if last reference is the current machine instruction being processed. This can happen when it is processing a physical register use and setting the current machine instruction as sub-register's last ref. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62617 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-20 21:25:12 +00:00
Evan Cheng
c99031b02a Add test case for PR3154. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62604 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-20 19:29:54 +00:00
Bill Wendling
20394494cc Testcase for limited precision stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62572 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-20 06:23:59 +00:00
Dan Gohman
f5add58549 Fix a dagcombine to not generate loads of non-round integer types, 
as its comment says, even in the case where it will be generating
extending loads. This fixes PR3216.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62557 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-20 01:06:45 +00:00
Evan Cheng
d0deec20f6 Make linear scan's trivial coalescer slightly more aggressive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62547 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-20 00:16:18 +00:00
Dale Johannesen
549170206e Move & restructure test per review. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62538 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-19 22:33:12 +00:00
Dan Gohman
dbe664adcd Fix SelectionDAG::ReplaceAllUsesWith to behave correctly when 
uses are added to the From node while it is processing From's
use list, because of automatic local CSE. The fix is to avoid
visiting any new uses.

Fix a few places in the DAGCombiner that assumed that after
a RAUW call, the From node has no users and may be deleted.

This fixes PR3018.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62533 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-19 21:44:21 +00:00
Dale Johannesen
1f54f58e64 compile-time fmod was done incorrectly. PR 3316. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62528 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-19 21:17:05 +00:00
Evan Cheng
2722e7b139 DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX instead of sign extending the low part (in AX/EAX/RAX) into it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62519 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-19 19:06:11 +00:00
Evan Cheng
a06ec9efe1 Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't 
optimize it to a SINT_TO_FP when the sign bit is known zero. X86 isel should perform the optimization itself.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62504 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-19 08:08:22 +00:00
Chris Lattner
d62284a804 Fix rdar://6505632, an llc crash on 483.xalancbmk 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62470 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-18 20:35:00 +00:00
Bill Wendling
959fb88949 Testcase for last commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62418 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-17 07:42:44 +00:00
Evan Cheng
8e27826649 Fix MatchAddress bug that's preventing negative displacement from being folded in 64-bit mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62413 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-17 07:09:27 +00:00
Mon P Wang
7ac9cdfc99 Simplify extract element of a scalar to vector. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62383 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-17 00:07:25 +00:00
Dan Gohman
3326f16036 Disable the post-RA scheduler on this test, since it uses a 
simple %prcontext which doesn't find what it's looking for
if the scheduler has rearranged the instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62363 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-16 21:40:12 +00:00
Evan Cheng
e57187cbe3 CreateVirtualRegisters does trivial copy coalescing. If a node def is used by a single CopyToReg, it reuses the virtual register assigned to the CopyToReg. This won't work for SDNode that is a clone or is itself cloned. Disable this optimization for those nodes or it can end up with non-SSA machine instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62356 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-16 20:57:18 +00:00
Bill Wendling
64e87326d9 Add support for non-zero __builtin_return_address values on X86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62338 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-16 19:25:27 +00:00
Mon P Wang
fa9c5eac33 Added missing support to widen an operand from a bit convert. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62285 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-15 22:43:38 +00:00
Mon P Wang
f0fcdd8e26 Expand insert/extract of a <4 x i32> with a variable index. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62281 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-15 21:10:20 +00:00
Rafael Espindola
bb46f52027 Add the private linkage. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62279 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-15 20:18:42 +00:00
Dan Gohman
f31408d75c Disable the register+memory forms of the bt instructions for now. Thanks 
to Eli for pointing out that these forms don't ignore the high bits of
their index operands, and as such are not immediately suitable for use
by isel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62194 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-01-13 23:23:30 +00:00