Commit Graph

11105 Commits

Author SHA1 Message Date
Jim Grosbach
7032f922b1 Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116534 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 22:57:13 +00:00
Jim Grosbach
792e9796b3 Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
pseudonym.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116512 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 20:43:44 +00:00
Jim Grosbach
1de588df69 MOVi16 and MOVT ARM mode encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116498 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 18:54:27 +00:00
Rafael Espindola
a0949b50dc Remove some code duplication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116484 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 16:34:44 +00:00
Mikhail Glushenkov
263cfecd4f Comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116476 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 13:43:20 +00:00
Bill Wendling
bbbdcd453d Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116471 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 02:33:26 +00:00
Bill Wendling
946a2740a5 Add encoding for 'fmstat'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116466 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 01:19:34 +00:00
Bill Wendling
88cf038436 - Add encodings for multiply add/subtract instructions in all their glory.
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116464 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 01:02:08 +00:00
Chris Lattner
a5bbde8efd fix a bug I introduced, no idea how this didn't repro right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116462 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 00:30:00 +00:00
Chris Lattner
15ea094474 hack to unbreak buildbots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116461 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 00:26:10 +00:00
Chris Lattner
eafc5cb80d add uadd_ov/usub_ov to apint, consolidate constant folding
logic to use the new APInt methods.  Among other things this
implements rdar://8501501 - llvm.smul.with.overflow.i32 should constant fold

which comes from "clang -ftrapv", originally brought to my attention from PR8221.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116457 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-14 00:05:07 +00:00
Jim Grosbach
b3af5de2d9 Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 21:00:04 +00:00
Bill Wendling
67a704de03 Add MC encodings for VCVT* instrunctions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116431 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 20:58:46 +00:00
Jim Grosbach
b35ad41fef Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 19:56:10 +00:00
Jim Grosbach
24989ecc70 Add ARM mode operand encoding information for ADDE/SUBE instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116412 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 18:00:52 +00:00
Rafael Espindola
6d8628061b Fix another case where we were preferring instructions with large
immediates instead of 8 bits ones.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116410 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 17:14:25 +00:00
Rafael Espindola
dba81cf40e Fix PR8365 by adding a more specialized Pat that checks if an 'and' with
8 bit constants can be used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116403 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 13:31:20 +00:00
Bill Wendling
6932643a37 Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test
just yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116386 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 01:17:33 +00:00
Bill Wendling
54908dd72b Add encodings for VCVT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116385 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 00:56:35 +00:00
Jim Grosbach
89c898f8af Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
arithmetic-with-carry-in instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116384 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 00:50:27 +00:00
Bill Wendling
1fc6d8837f Add VCMPZ and VABS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116383 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 00:38:07 +00:00
Bill Wendling
cd77686254 Refactor VCMP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116379 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13 00:04:29 +00:00
Eric Christopher
8f9145b0eb FileCheckize this in a hope to quiet a valgrind warning on grep.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116376 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:47:58 +00:00
Bill Wendling
5a1fd8cf68 Add encodings for VNMUL[SD].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116375 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:47:37 +00:00
Bill Wendling
caa3d467ab Add encodings for VDIV and VMUL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116370 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:22:27 +00:00
Jim Grosbach
c14b80f6d3 Be nitpicky and line up the comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116365 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:14:03 +00:00
Bill Wendling
dd3bc112e6 Add encoding for VSUB and VCMP.
Fear not! I'm going to try a refactoring right now. :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116359 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 22:55:35 +00:00
Bill Wendling
6e8bf26342 Don't need to specify calling convention. Add 'readnone' to functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 22:24:10 +00:00
Bill Wendling
174777bb2b Encoding for VADDD. Plus a test for the VFP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 22:08:41 +00:00
Jim Grosbach
0de6ab3c43 Add encoding information for the remainder of the generic arithmetic
ARM instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116313 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 17:11:26 +00:00
Dan Gohman
c015723131 Add a simple testcase for tbaa.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116272 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 23:54:13 +00:00
Jim Grosbach
42fac8ee3b MC machine encoding for simple aritmetic instructions that use a shifted
register operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116259 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 23:16:21 +00:00
Andrew Trick
0a434dbb91 PR8297
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116223 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 21:08:42 +00:00
Jakob Stoklund Olesen
4f9af2ef65 PowerPC varargs functions store live-in registers on the stack. Make sure we use
virtual registers for those stores since RegAllocFast requires that each live
physreg only be used once.

This fixes PR8357.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116222 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 20:43:09 +00:00
Eric Christopher
8ff9a9da0a Found a bug turning this on by default. Disable again for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116220 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 20:26:21 +00:00
Eric Christopher
a3d210733a Remove now non-existent option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116219 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 20:21:21 +00:00
Andrew Trick
1a2cf3b4d9 Fixes bug 8297: i386 cmpxchg8b, missing MachineMemOperand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116214 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 19:02:04 +00:00
Chris Lattner
60cb528246 Per discussion with Sanjiv, remove the PIC16 target from mainline. When/if
it comes back, it will be largely a rewrite, so keeping the old codebase
in tree isn't helping anyone.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116190 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 05:44:40 +00:00
Michael J. Spencer
92bf38c956 X86: MinGW should always use libgcc on Windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116177 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-10 23:11:06 +00:00
Michael J. Spencer
1802a9f8fe X86: Call _alldiv instead of __divdi3 on Windows (excluding cygwin).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116174 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-10 22:04:34 +00:00
Chris Lattner
27287664c2 force a triple, varargs isn't supported with the SVR4 ABI the buildbot tells me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116170 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-10 18:59:01 +00:00
Chris Lattner
749dc72bdc fix the expansion of va_arg instruction on PPC to know the arg
alignment for PPC32/64, avoiding some masking operations.

llvm-gcc expands vaarg inline instead of using the instruction
so it has never hit this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116168 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-10 18:34:00 +00:00
Kenneth Uildriks
74fa7327d6 Now using a variant of the existing inlining heuristics to decide whether to create a given specialization of a function in PartialSpecialization. If the total performance bonus across all callsites passing the same constant exceeds the specialization cost, we create the specialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116158 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09 22:06:36 +00:00
Michael J. Spencer
28ca86aa19 MC-COFF: Fix .bss section size. Fixes PR8335. Patch by NAKAMUTA Takumi!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116155 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09 16:04:45 +00:00
Benjamin Kramer
2e09a25c0b Don't test a removed function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116154 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09 15:53:25 +00:00
Michael J. Spencer
192d136750 MC-COFF: Implement InitSections. Fixes PR8335.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116151 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09 15:44:27 +00:00
Michael J. Spencer
7d4900416a MC-COFF: Add COFFAsmParser. Completes PR8343.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116150 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09 11:01:07 +00:00
Evan Cheng
d2ca813549 Correct some load / store instruction itinerary mistakes:
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116134 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09 01:03:04 +00:00
Bill Wendling
5ed5c38423 Simplify test and move into a generic "crash" ll file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116130 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09 00:29:04 +00:00
Bill Wendling
0aa38b9381 Check to make sure that the iterator isn't at the beginning of the basic block
before decrementing. <rdar://problem/8529919>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116126 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-09 00:03:48 +00:00