Commit Graph

81439 Commits

Author SHA1 Message Date
Bill Wendling
76b13ed403 Cleanup whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153804 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31 10:50:14 +00:00
Bill Wendling
caf71d4185 Free the codegen options when deleting LTO code generator object.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153803 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31 10:49:43 +00:00
Bill Wendling
168f142834 Cleanup whitespace and remove unneeded 'extern' keyword on function definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153802 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31 10:44:20 +00:00
Chandler Carruth
426d5715b1 Clean up the naming in this test. Someone pointed this out in review at
one point, and I forgot to go back and clean it up. Sorry about that. =/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153801 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31 10:38:48 +00:00
Chandler Carruth
c3e955927f FileCheck-ize this test, and generally tidy it up prior to changing
things around.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153799 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31 09:22:33 +00:00
Duncan Sands
4000afe712 I noticed in passing that the Metadata getIfExists method was creating a new
node and returning it if one didn't exist.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153798 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31 08:20:11 +00:00
Hal Finkel
6173ed95da Correctly vectorize powi.
The powi intrinsic requires special handling because it always takes a single
integer power regardless of the result type. As a result, we can vectorize
only if the powers are equal. Fixes PR12364.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153797 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31 03:38:40 +00:00
Andrew Trick
9f2a9d741f comment typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153796 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31 02:39:17 +00:00
Akira Hatanaka
b2874df81d Select static relocation model if it is jitting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153795 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31 02:38:36 +00:00
Andrew Trick
dd9a50196c Introduce Register Units: Give each leaf register a number.
First small step toward modeling multi-register multi-pressure. In the
future, register units can also be used to model liveness and
aliasing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153794 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31 01:35:59 +00:00
Jakob Stoklund Olesen
3ee3661f8f Add a 2 byte safety margin in offset computations.
ARMConstantIslandPass still has bugs where jump table compression can
cause constant pool entries to go out of range.

Add a safety margin of 2 bytes when placing constant islands, but use
the real max displacement for verification.

<rdar://problem/11156595>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153789 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31 00:06:44 +00:00
Jakob Stoklund Olesen
101c03a8c9 Add more debugging output to ARMConstantIslandPass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153788 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31 00:06:42 +00:00
Bill Wendling
5ff4bc20a1 * Set the scope attributes for the ASM symbol we added to be the value passed
into the function.
* Reorder some header files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153783 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 23:26:06 +00:00
Benjamin Kramer
cef670a3a3 Rip out emission of the regIsInRegClass function for the asm printer.
It's slow, bloated and completely redundant with MCRegisterClass::contains.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153782 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 23:13:40 +00:00
Jim Grosbach
bf3c322640 ARM fix encoding fixup resolution for ldrd and friends.
The 8-bit payload is not contiguous in the opcode. Move the upper nibble
over 4 bits into the correct place.

rdar://11158641

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153780 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 21:54:22 +00:00
Jakob Stoklund Olesen
c19f72bd83 Use SequenceToOffsetTable in emitRegisterNameString.
This allows suffix sharing in register names. (AX is a suffix of EAX).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153777 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 21:12:52 +00:00
Jakob Stoklund Olesen
0d4e2ea00e Reapply 153764 and 153761 with a fix.
Use an explicit comparator instead of the default.

The sets are sorted, but not using the default comparator. Hopefully,
this will unbreak the Linux builders.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153772 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 20:24:14 +00:00
Rafael Espindola
77ff8bbc2a Revert 153764 and 153761. They broke a --enable-optimized --enable-assertions
--enable-expensive-checks build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153771 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 20:09:06 +00:00
Jim Grosbach
ad353c6303 ARM assembler should prefer non-aliases encoding of cmp.
When an immediate is both a value [t2_]so_imm and a [t2_]so_imm_neg,
we want to use the non-negated form to make sure we prefer the normal
encoding, not the aliased encoding via the negation of, e.g., 'cmp.w'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153770 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 19:59:02 +00:00
Jim Grosbach
a45e3747e6 ARM encoding for VSWP got the second operand incorrect.
Make the non-tied register operand names line up with what the base
class encoding handler expects.

rdar://11157236

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153766 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 18:53:01 +00:00
Jim Grosbach
8f1148bd07 ARM can only use narrow encoding for low regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153765 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 18:39:43 +00:00
Jakob Stoklund Olesen
ecf2d9fc0d Compress SimpleValueType lists by sharing.
Many register classes have the same value types. Share the table space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153764 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 17:42:04 +00:00
Jakob Stoklund Olesen
8f36b0b139 Compress register lists by sharing suffixes.
TableGen emits lists of sub-registers, super-registers, and overlaps. Put
them all in a single table and use a SequenceToOffsetTable to share
suffixes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153761 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 17:25:43 +00:00
Jakob Stoklund Olesen
184440e808 Add a SequenceToOffsetTable to TableGen.
This is similar to the StringToOffsetTable we use to produce string
tables, but it can be used for other sequences than strings, and it
eliminates entries for suffixes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153760 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 17:25:40 +00:00
Jim Grosbach
2d30d947ec ARM integrated assembler should encoding choice for add/sub imm.
For 'adds r2, r2, #56' outside of an IT block, the 16-bit encoding T2
can be used for this syntax. Prefer the narrow encoding when possible.

rdar://11156277

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153759 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 17:20:40 +00:00
Rafael Espindola
092c5ccf5b Handle unreachable code in the dominates functions. This changes users when
needed for correctness, but still doesn't clean up code that now unnecessary
checks for reachability.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153755 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 16:46:21 +00:00
Danil Malyshev
0e4fa5ff36 Re-factored RuntimeDyLd:
1. The main works will made in the RuntimeDyLdImpl with uses the ObjectFile class. RuntimeDyLdMachO and RuntimeDyLdELF now only parses relocations and resolve it. This is allows to make improvements of the RuntimeDyLd more easily. In addition the support for COFF can be easily added.

2. Added ARM relocations to RuntimeDyLdELF.

3. Added support for stub functions for the ARM, allowing to do a long branch.

4. Added support for external functions that are not loaded from the object files, but can be loaded from external libraries. Now MCJIT can correctly execute the code containing the printf, putc, and etc.

5. The sections emitted instead functions, thanks Jim Grosbach. MemoryManager.startFunctionBody() and MemoryManager.endFunctionBody() have been removed.
6. MCJITMemoryManager.allocateDataSection() and MCJITMemoryManager. allocateCodeSection() used JMM->allocateSpace() instead of JMM->allocateCodeSection() and JMM->allocateDataSection(), because I got an error: "Cannot allocate an allocated block!" with object file contains more than one code or data sections.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153754 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 16:45:19 +00:00
Jim Grosbach
c0164f8608 ARM assembly parsing needs to be paranoid about negative immediates.
Make sure to treat immediates as unsigned when doing relative comparisons.

rdar://11153621

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153753 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 16:31:31 +00:00
Rafael Espindola
7c7121edb9 Add computeMaskedBitsLoad back, as it was the change to instsimplify that
caused the slowdown last time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153747 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 15:52:11 +00:00
Benjamin Kramer
2f1abe9a5f Add a note about a missed cmov -> sbb opportunity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153741 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 13:02:58 +00:00
Bill Wendling
8fd3fcdba8 Cleanup whitespace. Doxygenize comments. And indent to llvm coding standards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153740 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 10:29:38 +00:00
James Molloy
cb0809b82b Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch.
Patch by Tim Northover!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153737 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 09:15:32 +00:00
Evan Cheng
1c80f56268 ARM target should allow codegenprep to duplicate ret instructions to enable tailcall opt. rdar://11140249
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153717 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 01:24:39 +00:00
Bill Wendling
c459d31164 Testcase for r153710.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153711 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 00:26:54 +00:00
Bill Wendling
4108bd3780 Add testcase for r153705
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153706 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 00:05:02 +00:00
Bill Wendling
84364a4e23 If we have a VLA that has a "use" in a metadata node that's then used
here but it has no other uses, then we have a problem. E.g.,

  int foo (const int *x) {
    char a[*x];
    return 0;
  }

If we assign 'a' a vreg and fast isel later on has to use the selection
DAG isel, it will want to copy the value to the vreg. However, there are
no uses, which goes counter to what selection DAG isel expects.
<rdar://problem/11134152>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153705 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30 00:02:55 +00:00
Lang Hames
f9e894d21d Change the constant in this testcase so that it results in a constant pool
load.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153704 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29 23:52:38 +00:00
Bill Wendling
288967dfac Revert r153694. It was causing failures in the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153701 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29 23:23:59 +00:00
Jakob Stoklund Olesen
7a4c071cd9 Invalidate liveness in ARMConstantIslandPass.
This pass splits basic blocks to insert constant islands, and it
doesn't recompute the live-in lists. No later passes depend on accurate
liveness information.

This fixes PR12410 where the machine code verifier was complaining.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153700 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29 23:14:26 +00:00
Jakob Stoklund Olesen
ccca22e9e2 Prefer even-odd D-register pairs.
We are sometimes allocatinog from the DPair register class which
contains odd-even pairs in addition to the Q registers.

Place the Q registers first in the DPair allocation order as they can be
copied with a single instruction. The odd-even pairs should only be
allocated as a last resort.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153699 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29 22:54:32 +00:00
Chandler Carruth
803d134007 Filecheck-ize this test so that it actually tests something reasonable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153697 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29 22:01:41 +00:00
Lang Hames
c0a9f820d8 Try using vmov.i32 to materialize FP32 constants that can't be materialized by
vmov.f32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153696 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29 21:56:11 +00:00
Danil Malyshev
4b0b8ef1b0 Re-factored RuntimeDyld.
Added ExecutionEngine/MCJIT tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153694 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29 21:46:18 +00:00
Eric Christopher
6c31ee2b10 Lowercase the tag name to match the rest of dwarf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153691 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29 21:35:05 +00:00
Jim Grosbach
b22e70d835 ARM assembly 'cmp lr, #0' should not encode using 'cmn'.
The CMP->CMN alias was matching for an immediate of zero when it
should only match for negative values.

rdar://11129224

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153689 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29 21:19:52 +00:00
Lang Hames
182c34b121 The shuffle scheduler is only available in asserts build - make misched-new.ll
testcase require asserts.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153687 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29 21:11:47 +00:00
Jakob Stoklund Olesen
85bdf2e76a Handle register copies for the new ARM register classes.
ARM recently gained DPair, DTriple, and DQuad register classes.
Update copyPhysReg() to handle copies in these register classes.

No test case, it is difficult to make the register allocator emit the
odd copies reliably. The missing DPair copy caused a failure on
partialsums in the nightly test suite.

<rdar://problem/11147997>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153686 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29 21:10:40 +00:00
Benjamin Kramer
e13cea4110 Drop O4 from the llc manpage, it was removed in r70445.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153684 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29 20:40:18 +00:00
Lang Hames
616c841946 Make x86 REP_MOV* and REP_STO instructions use the correct operand sizes in 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153680 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29 19:54:28 +00:00
Danil Malyshev
95c677eef6 Fix missed files in JIT unittests Makefile
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153672 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29 18:53:15 +00:00