6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-11 09:29:20 +00:00
Code Issues Projects Releases Wiki Activity
97,788 Commits 39 Branches 0 Tags 277 MiB
80ccd9ea59
Commit Graph

59 Commits

Author SHA1 Message Date
NAKAMURA Takumi
f3ad574568 Prune trailing linefeeds. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193511 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-28 04:07:31 +00:00
Jyotsna Verma
36e1b51438 Hexagon: Add patterns to generate 'combine' instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181805 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-14 17:16:38 +00:00
Jyotsna Verma
1a35b8e2eb Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181624 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-10 20:27:34 +00:00
Jyotsna Verma
8cc93593cd Hexagon: Set accessSize and addrMode on all load/store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181324 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-07 15:06:29 +00:00
Jyotsna Verma
1a7eab3878 Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181235 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-06 18:49:23 +00:00
Jyotsna Verma
d4f8a6b9e9 reverting r180953 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180964 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-02 22:10:59 +00:00
Jyotsna Verma
8a3f50038f Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180953 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-02 21:21:57 +00:00
Jyotsna Verma
6ea706e40e Hexagon: Use multiclass for Jump instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180885 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-01 21:37:34 +00:00
Jyotsna Verma
42ba77db53 Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180145 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-23 21:17:40 +00:00
Jyotsna Verma
197c833ee1 Hexagon: Define relations for GP-relative instructions. 
No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180144 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-23 21:05:55 +00:00
Jyotsna Verma
3d7b39e7d4 Hexagon: Remove duplicate instructions to handle global/immediate values 
for absolute/absolute-set addressing modes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180120 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-23 17:11:46 +00:00
Jyotsna Verma
1877dc00e7 Hexagon: Set isPredicatedNew flag on predicate new instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179388 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-12 18:01:06 +00:00
Jyotsna Verma
c1406d76ec Hexagon: Set isPredicatedFlase flag for all the instructions with negated predication. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179387 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-12 17:46:52 +00:00
Jyotsna Verma
4f2ef94d6a Hexagon: Use multiclass for gp-relative instructions. 
Remove noV4T gp-relative instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178246 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-28 16:25:57 +00:00
Jyotsna Verma
7bb9585c6e Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178032 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-26 15:43:57 +00:00
Jyotsna Verma
97e602b574 Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and word. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177747 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-22 18:41:34 +00:00
Jyotsna Verma
86df21767a Hexagon: Add patterns for zero extended loads from i1->i64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176689 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-08 14:15:15 +00:00
Jyotsna Verma
b6716187ca Hexagon: Add support to lower block address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176637 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-07 19:10:28 +00:00
Jyotsna Verma
0d44328ce8 reverting patch 176508. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176513 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-05 20:29:23 +00:00
Jyotsna Verma
c34f17140f Hexagon: Add support for lowering block address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176508 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-05 19:37:46 +00:00
Jyotsna Verma
55a98b00c1 Hexagon: Set appropriate TSFlags to the loads/stores with global address to 
support constant extension.

This patch doesn't introduce any functionality changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175280 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-15 17:52:07 +00:00
Jyotsna Verma
5e3100afef Hexagon: Use multiclass for absolute addressing mode loads. 
This patch doesn't introduce any functionality changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175187 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-14 18:15:29 +00:00
Jyotsna Verma
f6563427c4 Hexagon: Use absolute addressing mode loads/stores for global+offset 
instead of redefining separate instructions for them.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175086 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-13 21:38:46 +00:00
Jyotsna Verma
1d3d2c57f5 Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle 
zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174429 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-05 19:20:45 +00:00
Jyotsna Verma
691c365aad Hexagon: Use multiclass for absolute addressing mode stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174412 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-05 18:15:34 +00:00
Jyotsna Verma
4210da7253 Hexagon: Add V4 compare instructions. Enable relationship mapping 
for the existing instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174389 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-05 16:42:24 +00:00
Jyotsna Verma
3e1635d08c Hexagon: Add V4 combine instructions and some more Def Pats for V2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174331 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-04 15:52:56 +00:00
Jyotsna Verma
924223c9ab Replace LDriu*[bhdw]_indexed_V4 instructions with "def Pats". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174193 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-01 16:36:16 +00:00
Jyotsna Verma
05f52eca94 Add appropriate TSFlags to the instructions that must be always extended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174186 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-01 15:54:43 +00:00
Jyotsna Verma
9c3846c99c Use multiclass for post-increment store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173816 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-29 18:42:41 +00:00
Jyotsna Verma
30c3bbe007 Add constant extender support for MInst type instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173813 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-29 18:18:50 +00:00
Craig Topper
a812641879 Remove more unnecessary # operators with nothing to paste proceeding them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171702 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-07 06:14:20 +00:00
Craig Topper
71ab7a79a7 Remove # from the beginning and end of def names. The # is a paste operator and should only be used with something to paste on either side. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171697 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-07 05:45:56 +00:00
Jyotsna Verma
82a36e2b59 Add constant extender support to GP-relative load/store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170672 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-20 06:52:46 +00:00
Jyotsna Verma
39498d1ff0 Add TSFlags to ALU32 type instructions for constant-extender/Relationship maps. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170671 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-20 06:45:39 +00:00
Jyotsna Verma
2d3b67ec0e Use multiclass for new-value store instructions with MEMri operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169814 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-11 05:12:25 +00:00
Jyotsna Verma
5807fd41a7 Define new-value store instructions with base+immediate addressing mode 
using multiclass.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169432 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-05 22:02:56 +00:00
Jyotsna Verma
61b632d9f7 Use multiclass to define store instructions with base+immediate offset 
addressing mode and immediate stored value.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169408 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-05 19:32:03 +00:00
Jyotsna Verma
e198626f87 Define store instructions with base+register offset addressing mode 
using multiclass.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169314 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-04 21:58:25 +00:00
Jyotsna Verma
4b3aafb4b2 Add patterns to define 'combine', 'tstbit', 'ct0/cl0' (count trailing/leading zeros) 
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169287 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-04 18:05:01 +00:00
Jyotsna Verma
bfeecc1306 Define store instructions with base+immediate offset addressing mode 
using multiclass.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169168 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-03 22:26:28 +00:00
Jyotsna Verma
b76c710aab Use multiclass for the store instructions with MEMri operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168983 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-30 06:10:22 +00:00
Jyotsna Verma
65502aa5fd Use multiclass for the load instructions with 'base + register offset' 
addressing mode.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168976 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-30 04:19:09 +00:00
Jyotsna Verma
7d1b42a842 Removing some unused instruction definitions from the Hexagon backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168388 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-20 22:14:23 +00:00
Jyotsna Verma
cb02fa9d7f Added multiclass for post-increment load instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167974 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-14 20:38:48 +00:00
Jakob Stoklund Olesen
68c10a2ff7 Remove variable_ops from call instructions in most targets. 
Call instructions are no longer required to be variadic, and
variable_ops should only be used for instructions that encode a variable
number of arguments, like the ARM stm/ldm instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160189 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-13 20:44:29 +00:00
Brendon Cahoon
5262abb268 Revert 156634 upon request until code improvement changes are made. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156775 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-14 19:35:42 +00:00
Brendon Cahoon
6d532d8860 Hexagon constant extender support. 
Patch by Jyotsna Verma.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156634 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 19:56:59 +00:00
Sirish Pande
ab3a7fb244 Update load/store instruction patterns in Hexagon V4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156411 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-08 19:50:20 +00:00
Sirish Pande
71d56462a1 Extensions of Hexagon V4 instructions. 
This adds new instructions for Hexagon V4 architecture.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156071 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-03 16:18:50 +00:00