Commit Graph

90862 Commits

Author SHA1 Message Date
Vincent Lejeune
88524e3f6c R600/SI: Share code recording ShaderTypeAttribute between generations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178504 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01 21:47:53 +00:00
Vincent Lejeune
8e59191eb8 R600: Emit CF_ALU and use true kcache register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178503 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01 21:47:42 +00:00
Eli Bendersky
19801a6481 Fix top-comment header and some indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178492 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01 19:47:56 +00:00
Hal Finkel
a1646ceb9a Fix a bad assert in PPCTargetLowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178489 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01 18:42:58 +00:00
Hal Finkel
6c81b118ca Add triple to test/CodeGen/PowerPC/stfiwx-2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178486 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01 18:18:44 +00:00
Shuxin Yang
ad26993e1a Correct assertion condition
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178484 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01 18:13:05 +00:00
Arnold Schwaighofer
f28a29b776 Merge load/store sequences with adresses: base + index + offset
We would also like to merge sequences that involve a variable index like in the
example below.

    int index = *idx++
    int i0 = c[index+0];
    int i1 = c[index+1];
    b[0] = i0;
    b[1] = i1;

By extending the parsing of the base pointer to handle dags that contain a
base, index, and offset we can handle examples like the one above.

The dag for the code above will look something like:

 (load (i64 add (i64 copyfromreg %c)
                (i64 signextend (i8 load %index))))

 (load (i64 add (i64 copyfromreg %c)
                (i64 signextend (i32 add (i32 signextend (i8 load %index))
                                         (i32 1)))))

The code that parses the tree ignores the intermediate sign extensions. However,
if there is a sign extension it needs to be on all indexes.

 (load (i64 add (i64 copyfromreg %c)
                (i64 signextend (add (i8 load %index)
                                     (i8 1))))
 vs

 (load (i64 add (i64 copyfromreg %c)
                (i64 signextend (i32 add (i32 signextend (i8 load %index))
                                         (i32 1)))))
radar://13536387

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178483 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01 18:12:58 +00:00
Hal Finkel
4647919784 Add more PPC floating-point conversion instructions
The P7 and A2 have additional floating-point conversion instructions which
allow a direct two-instruction sequence (plus load/store) to convert from all
combinations (signed/unsigned i32/i64) <--> (float/double) (on previous cores,
only some combinations were directly available).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178480 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01 17:52:07 +00:00
Hal Finkel
a1f4290ac9 Use ImmToIdxMap.count in PPCRegisterInfo
Code improvement suggested by Jakob (in review of r178450). No functionality
change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178473 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01 17:02:06 +00:00
Hal Finkel
dc8efbae14 Fix PowerPC/cttz.ll to specify a cpu (and use FileCheck)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178472 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01 16:31:56 +00:00
Hal Finkel
1fce88313e Add the PPC popcntw instruction
The popcntw instruction is available whenever the popcntd instruction is
available, and performs a separate popcnt on the lower and upper 32-bits.
Ignoring the high-order count, this can be used for the 32-bit input case
(saving on the explicit zero extension otherwise required to use popcntd).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178470 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01 15:58:15 +00:00
Nadav Rotem
953783e00c Add support for vector data types in the LLVM interpreter.
Patch by:
Veselov, Yuri <Yuri.Veselov@intel.com>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178469 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01 15:53:30 +00:00
Hal Finkel
f170cc9b2e Treat PPCISD::STFIWX like the memory opcode that it is
PPCISD::STFIWX is really a memory opcode, and so it should come after
FIRST_TARGET_MEMORY_OPCODE, and we should use DAG.getMemIntrinsicNode to create
nodes using it.

No functionality change intended (although there could be optimization benefits
from preserving the MMO information).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178468 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01 15:37:53 +00:00
Duncan Sands
0857a6fd33 Remove unused typedef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178462 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01 13:46:15 +00:00
Arnold Schwaighofer
55097ff567 ARM Scheduler Model: Add resources instructions, map resources in subtargets
Reapply r177968:
After commit 178074 we can now have undefined scheduler variants.

Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define
resource mappings under the CortexA9 SchedModel. Define resources and mappings
for the SwiftModel.

Incooperate Andrew's feedback.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178460 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01 13:07:05 +00:00
Benjamin Kramer
13497b3aa7 X86TTI: Add accurate costs for itofp operations, based on the actual instruction counts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178459 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01 10:23:49 +00:00
Joe Abbey
ef7964c1b7 Whitespace cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178454 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-01 02:28:07 +00:00
Vincent Lejeune
2691fe98a7 R600: Emit native instructions for tex
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178452 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-31 19:33:04 +00:00
Duncan Sands
79f615cbfe There is no longer any need to silence this compiler warning as the warning has
been turned off globally.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178451 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-31 17:44:09 +00:00
Hal Finkel
4345e8040f Cleanup ImmToIdxMap and noImmForm in PPCRegisterInfo
ImmToIdxMap should be a DenseMap (not a std::map) because there
is no ordering requirement. Also, we don't need a separate list
of instructions for noImmForm in eliminateFrameIndex, because this
list is essentially the complement of the keys in ImmToIdxMap.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178450 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-31 14:43:31 +00:00
Benjamin Kramer
b8f0d89d05 X86: Promote sitofp <8 x i16> to <8 x i32> when AVX is available.
A vector sext + sitofp is a lot cheaper than 8 scalar conversions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178448 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-31 12:49:15 +00:00
Hal Finkel
8049ab15e4 Add the PPC lfiwax instruction
This instruction is available on modern PPC64 CPUs, and is now used
to improve the SINT_TO_FP lowering (by eliminating the need for the
separate sign extension instruction and decreasing the amount of
needed stack space).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178446 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-31 10:12:51 +00:00
Hal Finkel
9ad0f4907b Cleanup PPC(64) i32 -> float/double conversion
The existing SINT_TO_FP code for i32 -> float/double conversion was disabled
because it relied on broken EXTSW_32/STD_32 instruction definitions. The
original intent had been to enable these 64-bit instructions to be used on CPUs
that support them even in 32-bit mode.  Unfortunately, this form of lying to
the infrastructure was buggy (as explained in the FIXME comment) and had
therefore been disabled.

This re-enables this functionality, using regular DAG nodes, but only when
compiling in 64-bit mode. The old STD_32/EXTSW_32 definitions (which were dead)
are removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178438 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-31 01:58:02 +00:00
Benjamin Kramer
0b68b758bb DAGCombine: visitXOR can replace a node without returning it, bail out in that case.
Fixes the crash reported in PR15608.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178429 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 21:28:18 +00:00
Justin Holewinski
531ebc8a3c Add start of user documentation for NVPTX
Summary: This is the beginning of user documentation for the NVPTX back-end.  I want to ensure I am integrating this properly into the rest of the LLVM documentation.

Differential Revision: http://llvm-reviews.chandlerc.com/D600

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178428 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 16:41:14 +00:00
Benjamin Kramer
42734cfb41 Change '@SECREL' suffix to GAS-compatible '@SECREL32'.
'@SECREL' is what is used by the Microsoft assembler, but GNU as expects '@SECREL32'.
With the patch, the MC-generated code works fine in combination with a recent GNU as (2.23.51.20120920 here).

Patch by David Nadlinger!
Differential Revision: http://llvm-reviews.chandlerc.com/D429

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178427 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 16:21:50 +00:00
Sean Silva
6ef362a6de [docs] llvmbugs is not the place for patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178426 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 15:33:02 +00:00
Sean Silva
fb7aa39435 [docs] Annotate mailing lists with their "name".
Nobody says "the developer's list" or "commits archive"; they always say
"llvmdev" or "llvm-commits". It makes sense for our documentation to
at least make that association explicitly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178425 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 15:33:01 +00:00
Sean Silva
135856526c [docs] Reorganize mailing lists.
Order them roughly by "which one should a newbie join first".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178424 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 15:32:54 +00:00
Sean Silva
bd1aecbea7 [docs] Pull IRC and Mailing Lists under a new "Community" heading.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178423 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 15:32:51 +00:00
Sean Silva
cad9b9cdb4 [docs] The GEP FAQ is not "design and overview"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178422 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 15:32:50 +00:00
Sean Silva
a6a22233a8 [docs] Put DeveloperPolicy under "Development Process Documentation"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178421 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 15:32:47 +00:00
Benjamin Kramer
ddcc82b871 Put private class into an anonmyous namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178420 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 15:23:08 +00:00
Justin Holewinski
b24fc1c7f7 [NVPTX] Remove support for SM < 2.0. This was never fully supported anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178417 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 14:29:30 +00:00
Justin Holewinski
21fdcb0271 [NVPTX] Add NVVMReflect pass to allow compile-time selection of
specific code paths.

This allows us to write code like:

  if (__nvvm_reflect("FOO"))
    // Do something
  else
    // Do something else

and compile into a library, then give "FOO" a value at kernel
compile-time so the check becomes a no-op.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178416 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 14:29:25 +00:00
Justin Holewinski
3639ce2575 [NVPTX] Run clang-format on all NVPTX sources.
Hopefully this resolves any outstanding style issues and gives us
an automated way of ensuring we conform to the style guidelines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178415 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 14:29:21 +00:00
Benjamin Kramer
a9f83517fc Object: Turn a couple of degenerate for loops into while loops.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 13:07:51 +00:00
Shuxin Yang
2d10010649 Implement XOR reassociation. It is based on following rules:
rule 1: (x | c1) ^ c2 => (x & ~c1) ^ (c1^c2),
     only useful when c1=c2
  rule 2: (x & c1) ^ (x & c2) = (x & (c1^c2))
  rule 3: (x | c1) ^ (x | c2) = (x & c3) ^ c3 where c3 = c1 ^ c2
  rule 4: (x | c1) ^ (x & c2) => (x & c3) ^ c1, where c3 = ~c1 ^ c2

 It reduces an application's size (in terms of # of instructions) by 8.9%.
 Reviwed by Pete Cooper. Thanks a lot!

 rdar://13212115  


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178409 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 02:15:01 +00:00
Akira Hatanaka
fd2cd0db97 [mips] Add patterns for DSP indexed load instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178408 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 02:14:45 +00:00
Akira Hatanaka
175f0fd99a [mips] Define reg+imm load/store pattern templates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178407 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 02:01:48 +00:00
Akira Hatanaka
2c2c33a167 [mips] Fix DSP instructions to have explicit accumulator register operands.
Check that instruction selection can select multiply-add/sub DSP instructions
from a pattern that doesn't have intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178406 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 01:58:00 +00:00
Akira Hatanaka
7e287bfb58 Remove unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178405 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 01:46:28 +00:00
Akira Hatanaka
d593a77b4c [mips] Move the code which does dag-combine for multiply-add/sub nodes to
derived class MipsSETargetLowering.

We shouldn't be generating madd/msub nodes if target is Mips16, since Mips16
doesn't have support for multipy-add/sub instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178404 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 01:42:24 +00:00
Akira Hatanaka
f5926fd844 [mips] Fix definitions of multiply, multiply-add/sub and divide instructions.
The new instructions have explicit register output operands and use table-gen
patterns instead of C++ code to do instruction selection.

Mips16's instructions are unaffected by this change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178403 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 01:36:35 +00:00
Akira Hatanaka
9cf0724cc3 [mips] Remove function getFPBranchCodeFromCond. Rename invertFPCondCodeAdd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178396 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 01:16:38 +00:00
Akira Hatanaka
2459afe697 Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178395 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 01:15:17 +00:00
Akira Hatanaka
dd958925b0 [mips] Add mips-specific nodes which will be used to select multiply and divide
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178394 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 01:14:04 +00:00
Akira Hatanaka
cbcdcfbda5 [mips] Implement getRepRegClassFor in MipsSETargetLowering. This function is
called in several places in ScheduleDAGRRList.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178393 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 01:12:05 +00:00
Akira Hatanaka
8f4d3800a7 [mips] Fix MipsSEInstrInfo::copyPhysReg, loadRegFromStack and storeRegToStack
to handle accumulator registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178392 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 01:08:05 +00:00
Akira Hatanaka
d6a77822a9 [mips] Expand pseudo load, store and copy instructions right before
callee-saved scan.

The code makes use of register's scavenger's capability to spill multiple
registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178391 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 01:04:11 +00:00