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Author SHA1 Message Date
Jim Grosbach
88d1bc832c Add parsing/encoding tests for ARM ORR instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135602 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 18:48:53 +00:00
Jim Grosbach
a678514459 Consolidate ARM NOP encoding test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135600 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 18:39:38 +00:00
Jim Grosbach
c3635c2e92 ARM parsing and encoding tests for MVN 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135599 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 18:37:08 +00:00
Jim Grosbach
ab40f4b737 ARM assembly parsing of MUL instruction. 
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135596 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 18:20:31 +00:00
Eli Friedman
0381c21d2d PR10421: Fix a straightforward bug in the widening logic for CONCAT_VECTORS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135595 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 18:14:33 +00:00
Benjamin Kramer
9d999f58e3 Initialize the EHFrameSection pointer to zero. 
This should fix the spurious buildbot errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135594 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 18:13:23 +00:00
Eric Christopher
91e7ccd98b Regenerate configure and friends for Chad. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135592 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 17:04:49 +00:00
Jay Foad
626f52d43d Fix a GCC warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135581 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 08:15:21 +00:00
Evan Cheng
34ad6db8b9 - Move CodeModel from a TargetMachine global option to MCCodeGenInfo. 
- Introduce JITDefault code model. This tells targets to set different default
  code model for JIT. This eliminates the ugly hack in TargetMachine where
  code model is changed after construction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135580 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 07:51:56 +00:00
Evan Cheng
4c8164813c Include MCRegisterInfo to eliminate a compilation warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135575 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 06:54:19 +00:00
Francois Pichet
59458483a5 Fix the CMake build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135573 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 06:35:24 +00:00
Evan Cheng
e76a33b956 Add MCObjectFileInfo and sink the MCSections initialization code from 
TargetLoweringObjectFileImpl down to MCObjectFileInfo.

TargetAsmInfo is done to one last method. It's *almost* gone!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135569 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 05:58:47 +00:00
Andrew Trick
86c98145b2 indvars: Added getInsertPointForUses to find a valid place to truncate the IV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135568 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 05:32:06 +00:00
Andrew Trick
13bcf2e68a indvars -disable-iv-rewrite: Add NarrowIVDefUse to cache def-use 
info. Holding Use* pointers is bad form even though it happened to
work in this case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135566 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 04:39:24 +00:00
NAKAMURA Takumi
e3345c4e4a X86Subtarget.h: Assume "x86_64-cygwin", though it has not been released yet, to appease test/CodeGen/X86 on cygwin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135564 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 04:02:20 +00:00
Eric Christopher
03c45f60f3 New pointer rotate test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135562 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 03:09:11 +00:00
Eric Christopher
cf1e967df2 Extra semi-colon. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135561 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 02:44:39 +00:00
Andrew Trick
9e92152f77 indvars test case for r135558. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135559 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 02:14:37 +00:00
Andrew Trick
f22d95749a indvars -disable-iv-rewrite fix: derived GEP IVs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135558 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 02:08:58 +00:00
Benjamin Kramer
e236dc6553 Don't leak CodeGenInfos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135555 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 01:27:58 +00:00
Akira Hatanaka
de9416e261 Change name of class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135550 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 00:53:09 +00:00
Akira Hatanaka
32b7ebb163 Define classes for definitions of atomic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135546 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 00:23:01 +00:00
Bill Wendling
c8dad112b4 Build and install the archive when building the Apple way. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135538 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 23:33:42 +00:00
Akira Hatanaka
db54826f20 Lower memory barriers to sync instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135537 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 23:30:50 +00:00
Evan Cheng
70955c2d12 Fix an obvious typo that's preventing x86 (32-bit) from using .literal16. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135535 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 23:14:32 +00:00
Eli Friedman
3610604086 PR10386: Don't try to split an edge from an indirectbr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135534 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 22:59:41 +00:00
Benjamin Kramer
14c92467e7 Fix off-by-one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135533 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 22:59:25 +00:00
Jim Grosbach
b29b4dd988 Tweak ARM assembly parsing and printing of MSR instruction. 
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 22:45:10 +00:00
Devang Patel
c8fcfc9cd9 Distinguish between two copies of one inlined variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135528 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 22:31:15 +00:00
Jim Grosbach
80d01dd3d1 ARM assembly parsing of MRS instruction. 
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135527 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 21:59:29 +00:00
Owen Anderson
f1a0090073 Enhance the FixedLengthDecoder to be able to generate plausible-looking decoders for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135524 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 21:06:00 +00:00
Akira Hatanaka
bdd83fe382 Change variable name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135522 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:56:53 +00:00
Jim Grosbach
ccfd9313d1 ARM assembly parsing for MRC/MRC2/MRRC/MRRC2. 
Add range checking to the immediate operands. Update tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135521 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:35:35 +00:00
Akira Hatanaka
cc7ecc7290 Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or 
ANDi, when the instruction does not have any immediate operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135520 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:34:00 +00:00
Jim Grosbach
2317fe1584 Move mr[r]c[2] ARM tests and tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135517 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:28:56 +00:00
Jim Grosbach
1a2be4db5b ARM testcases for MOVT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135516 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:23:25 +00:00
Akira Hatanaka
4061da1403 Use descriptive variable names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135514 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:11:17 +00:00
Jim Grosbach
5f16057d1e ARM assembly parsing for MOV (register). 
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135513 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:10:31 +00:00
Jim Grosbach
558b66d3cd Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135507 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 19:47:11 +00:00
Jim Grosbach
731f209794 Tighten conditional for 'mov' cc_out. 
Make sure we only clobber the cc_out operand if it is indeed a default
non-setting operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135506 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 19:45:44 +00:00
Devang Patel
23336b449e Reapply r135457. This needs llvm-gcc change, that I forgot to check-in yesterday. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135504 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 19:41:54 +00:00
Jim Grosbach
ffa3225e26 ARM assembly parsing for MOV (immediate). 
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135500 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 19:13:28 +00:00
Jim Grosbach
0ec2aa21d0 Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135499 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 19:02:39 +00:00
Jim Grosbach
5a18700470 Remove unused code. 
cc_out and pred operands are added during parsing via custom C++ now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135497 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 18:32:48 +00:00
Akira Hatanaka
29af0918ce Fix comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135496 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 18:19:40 +00:00
Akira Hatanaka
70564a9c19 Remove redundant instructions. 
- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
  instruction being expanded, instead of masking it in thisMBB. 
- Remove redundant Or in EmitAtomicCmpSwap. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135495 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 18:14:26 +00:00
Akira Hatanaka
81b441151f Separate code that modifies control flow from code that adds instruction to 
basic blocks.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135490 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 17:09:53 +00:00
Jim Grosbach
6bc1dbc376 ARM range checking for so_imm operands in assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135489 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 16:50:30 +00:00
Bob Wilson
f51bb7cef8 Revert "Make a provision to encode inline location in a variable. This will enable dwarf writer to easily distinguish between two instances of a inlined variable in one basic block." 
This reverts commit 9fec5e346e.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135486 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 16:32:50 +00:00
Bob Wilson
66fc541abe Revert "Update docs to reflect r135457." 
This reverts commit ba034c0a2e.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135485 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 16:31:58 +00:00