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603 Commits

Author SHA1 Message Date
Evan Cheng
3bda20112e Eliminate or_not_add and just use AddedComplexity so isel tries or_is_add patterns first. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93245 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-12 18:31:19 +00:00
Dan Gohman
f1b4d26e67 Reapply the MOV64r0 patch, with a fix: MOV64r0 clobbers EFLAGS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93229 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-12 04:42:54 +00:00
Evan Cheng
199c4240fe Extend r93152 to work on OR r, r. If the source set bits are known not to overlap, then select as an ADD instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93191 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 22:03:29 +00:00
Evan Cheng
05920b8146 Revert 93158. It's breaking quite a few x86_64 tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93185 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 21:13:41 +00:00
Evan Cheng
ac000fa0ed Do not turn 8-bit OR to ADD since ADD8ri is not 3-addressfiable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93182 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 20:18:04 +00:00
Dan Gohman
71c25b7d7b Re-instate MOV64r0 and MOV16r0, with adjustments to work with the 
new AsmPrinter. This is perhaps less elegant than describing them
in terms of MOV32r0 and subreg operations, but it allows the
current register to rematerialize them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93158 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 17:37:57 +00:00
Dan Gohman
7e0d64a49c Pattern top-level operators don't need to be restricted to a 
single user. The _su forms are intended for non-top-level nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93155 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 17:21:05 +00:00
Evan Cheng
4b0345be30 Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93152 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 17:03:47 +00:00
Evan Cheng
b093bd0565 Fix what looks to me obvious instruction definition bugs. 
1. CMPXCHG8B and CMPXCHG16B did not specify implicit physical register defs and uses.
2. LCMPXCHG8B is loading 64 bit memory, not 32 bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92985 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-08 01:29:19 +00:00
Dan Gohman
4361bbfd0e Remove the SDNPAssociative properties for the flags-producing 
operators. Eli pointed out that it's not obvious what that
would mean.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92555 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-05 00:44:20 +00:00
Dan Gohman
43ffe6769a Add SDNPCommutative and SDNPAssociative to several X86 target nodes. 
This lets isel fold loads into them in more cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92506 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-04 20:51:05 +00:00
Eli Friedman
ba7b1c4db4 PR5886: Make sure IMUL32m is marked as setting EFLAGS, so scheduling doesn't 
do illegal stuff around it.  No testcase because the issue is very fragile.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92167 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-26 20:08:30 +00:00
Chris Lattner
ac105c4dca really remove the instruction, don't just comment it out 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91976 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 01:46:40 +00:00
Chris Lattner
9e3238303c completely eliminate the MOV16r0 'instruction'. The only 
interesting part of this is the divrem changes, which are
already tested by CodeGen/X86/divrem.ll.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91975 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 01:45:04 +00:00
Chris Lattner
6a38182471 stop pattern matching 16-bit zero's of a register to MOV16r0, 
instead use the appropriate subreggy thing.  This generates identical
code on some large apps (thanks to Evan's cross class coalescing
stuff he did back in july).  This means that MOV16r0 can go away
completely in the future soon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91972 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 01:30:26 +00:00
Evan Cheng
b1f4981333 Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91910 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 17:47:23 +00:00
Evan Cheng
400073d546 On recent Intel u-arch's, folding loads into some unary SSE instructions can 
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.

movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0

instead of
cvtss2sd (%rdi), %xmm0

An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91672 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 07:40:29 +00:00
Sean Callanan
108934c65d Instruction fixes, added instructions, and AsmString changes in the 
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 00:01:26 +00:00
Evan Cheng
2e489c4f9d Re-enable 91381 with fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91489 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-16 00:53:11 +00:00
Evan Cheng
ad9c0a3d8b Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91381 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 00:53:42 +00:00
Evan Cheng
15b0d97068 Fix an obvious bug. No test case since LEA16r is not being used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91219 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-12 18:51:56 +00:00
Dan Gohman
39a1fab856 Minor whitespace fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90166 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-30 23:33:53 +00:00
Dan Gohman
735afe14ee Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used. 
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89711 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-23 23:20:51 +00:00
Dan Gohman
e94975ee64 Use a tab in INT3's asm string, for consistency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86850 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-11 18:07:16 +00:00
Anton Korobeynikov
3a639a07ea Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364. 
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85766 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 00:11:39 +00:00
Dan Gohman
f705adbe5e Initial x86 support for BlockAddresses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85557 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 01:28:02 +00:00
Dan Gohman
533297b58d Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-29 18:10:34 +00:00
Dan Gohman
bab42bdd87 Following r84485, add Defs = [EFLAGS] to the 32-bit lock instructions too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84652 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 18:14:49 +00:00
Chris Lattner
172862a2a7 remove strings from instructions who are never asmprinted. 
All of these "subreg32" modifier instructions are handled
explicitly by the MCInst lowering phase.  If they got to
the asmprinter, they would explode.  They should eventually
be replace with correct use of subregs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84526 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 19:51:42 +00:00
Chris Lattner
71c7ace54f remove the asmstring, it is now dead. Improve comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82390 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-20 07:32:00 +00:00
Chris Lattner
b3c8547cb8 kill off printPICLabel now, it's specialness is handled by 
the MachineInstr ->MCInst lowering process, not in the 
asmprinter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82388 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-20 07:28:26 +00:00
Chris Lattner
e895c61515 Add an intel syntax MCInstPrinter implementation. You can now 
transcode from AT&T to intel syntax with "llvm-mc foo.s -output-asm-variant=1"



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82385 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-20 07:17:49 +00:00
Dan Gohman
e220c4b3d9 Add support for using the FLAGS result of or, xor, and and instructions 
on x86, to avoid explicit test instructions. A few existing tests changed
due to arbitrary register allocation differences.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82263 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-18 19:59:53 +00:00
Sean Callanan
a2dc2825fc Added RCL and RCR (rotate left and right with a 
carry bit) instructions to the Intel instruction
tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82260 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-18 19:35:23 +00:00
Sean Callanan
9a86f10875 Added the LODS (load byte into register, usually 
as part string parsing) instructions to the Intel
instruction tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82089 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-16 22:59:28 +00:00
Sean Callanan
358f1ef765 Added the LAR (load segment access rights) 
instructions to the Intel instruction tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82084 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-16 21:55:34 +00:00
Sean Callanan
7e6d727c9b Added the LOOP family of instructions to the Intel 
instruction tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82083 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-16 21:50:07 +00:00
Sean Callanan
d2125a03af Added an alternate form of register-register CMP 
to the Intel instruction tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82081 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-16 21:11:23 +00:00
Sean Callanan
8d70854dd8 Added the ENTER instruction, which sets up a stack 
frame, to the Intel instruction tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81995 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-16 02:57:13 +00:00
Sean Callanan
13cf8e9b82 Added the definitions for one-bit left shifts to 
the Intel instruction tables.

The patterns will stay blank because ADD reg, reg
is faster, but having the encoding available is
useful for the disassembler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81994 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-16 02:28:43 +00:00
Sean Callanan
356aed540c Added far return instructions (that is, returns to 
code in other segments) to the Intel instruction
tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81953 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-15 23:37:51 +00:00
Sean Callanan
62c28e3f91 Updated comments per Eli's suggestion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81923 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-15 21:43:27 +00:00
Sean Callanan
37be5903a6 Added register-to-register ADD instructions to the 
Intel tables, where the source operand is
specified by the R/M field and the destination
operand by the Reg field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81914 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-15 20:53:57 +00:00
Sean Callanan
38fee0edcf Added a new register class for segment registers 
to the Intel register table.
Added 16- and 64-bit MOVs to and from the segment
registers to the Intel instruction tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81895 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-15 18:47:29 +00:00
Sean Callanan
76f14be685 Modified the Intel instruction tables to include 
versions of CALL and JMP with segmented addresses
provided in-line, as pairs of immediates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81818 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-15 00:35:17 +00:00
Sean Callanan
2a46f3678e Added the WAIT instruction to the Intel tables, 
for the purposes of the disassembler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81603 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-12 02:52:41 +00:00
Sean Callanan
6f8f462ba5 Added CMPS (string comparison) instructions for all 
operand widths to the Intel instruction tables, for
the purposes of the disassembler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81601 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-12 02:25:20 +00:00
Sean Callanan
a82e4656b0 Added SCAS instructions in their 8, 16, 32, and 
64-bit variants for the disassembler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81591 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-12 00:37:19 +00:00
Sean Callanan
d00025a6c8 Added ADC, SUB, SBB, and OR instructions that operate 
on rAX and an immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81551 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-11 19:01:56 +00:00
Sean Callanan
7893ec6494 Added XOR instructions for rAX and immediates of 
various widths.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81458 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-10 19:52:26 +00:00