Commit Graph

21532 Commits

Author SHA1 Message Date
b9f69a41fc Test for commit access.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150178 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09 15:20:33 +00:00
3015dfb7d7 Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150169 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09 10:56:31 +00:00
f41ab77847 More tweaks to get the size of the X86 disassembler tables down.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150167 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09 08:58:07 +00:00
ce8f4c58d8 Flatten some of the arrays in the X86 disassembler tables to reduce space needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150161 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09 07:45:30 +00:00
450b3850ce Handle register masks when searching for EFLAGS clobbers.
Calls clobber the flags, but when using register masks there is no
EFLAGS<imp-def> operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150117 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-09 00:17:22 +00:00
1dd8c8560d Codegen pass definition cleanup. No functionality.
Moving toward a uniform style of pass definition to allow easier target configuration.
Globally declare Pass ID.
Globally declare pass initializer.
Use INITIALIZE_PASS consistently.
Add a call to the initializer from CodeGen.cpp.
Remove redundant "createPass" functions and "getPassName" methods.

While cleaning up declarations, cleaned up comments (sorry for large diff).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150100 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 21:23:13 +00:00
32986572bf Move pass configuration out of pass constructors: StackSlotColoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150097 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 21:22:57 +00:00
c7d081b594 Move pass configuration out of pass constructors: PostRAScheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150096 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 21:22:53 +00:00
61f1e3db43 Move pass configuration out of pass constructors: BranchFolderPass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150095 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 21:22:48 +00:00
ffea03f216 Added TargetPassConfig::setOpt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150093 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 21:22:39 +00:00
d2a7bedbc9 Move pass configuration out of pass constructors: TailDuplicate::PreRegAlloc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150091 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 21:22:30 +00:00
c635ebdb1a Use TSFlag bit to describe instruction properties.
Creating the isPredicated TSFlag enables the code
to use the property defined in the instruction format
instead of using a large switch statement.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150078 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 18:25:47 +00:00
f602040c49 Fixed a bug in printing "cmp" pseudo ops.
> This IR code
> %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 14)
> fails with assertion:
>
> llc: X86ATTInstPrinter.cpp:62: void llvm::X86ATTInstPrinter::printSSECC(const llvm::MCInst*, unsigned int, llvm::raw_ostream&): Assertion `0 && "Invalid ssecc argument!"' failed.
> 0  llc             0x0000000001355803
> 1  llc             0x0000000001355dc9
> 2  libpthread.so.0 0x00007f79a30575d0
> 3  libc.so.6       0x00007f79a23a1945 gsignal + 53
> 4  libc.so.6       0x00007f79a23a2f21 abort + 385
> 5  libc.so.6       0x00007f79a239a810 __assert_fail + 240
> 6  llc             0x00000000011858d5 llvm::X86ATTInstPrinter::printSSECC(llvm::MCInst const*, unsigned int, llvm::raw_ostream&) + 119

I added the full testing for all possible pseudo-ops of cmp.
I extended X86AsmPrinter.cpp and X86IntelInstPrinter.cpp.

You'l also see lines alignments (unrelated to this fix) in X86IselLowering.cpp from my previous check-in.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150068 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 08:37:26 +00:00
bc0e4bf754 Remove a couple unneeded intrinsic patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150067 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 08:29:30 +00:00
5a313bb7e8 Remove GCC builtins for vpermilp* intrinsics as clang no longer needs them. Custom lower the intrinsics to the vpermilp target specific node and remove intrinsic patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150060 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 06:36:57 +00:00
743e19983e [fast-isel] Add support for SUBs with non-legal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150047 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 02:45:44 +00:00
6fde875621 [fast-isel] Add support for ORs with non-legal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150045 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 02:29:21 +00:00
60c8fa6bb9 [fast-isel] Add support for indirect branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150014 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-07 23:56:08 +00:00
de1df103b9 Use LEA to adjust stack ptr for Atom. Patch by Andy Zhang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150008 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-07 22:50:41 +00:00
4ee1c5cf6c Do not fold ADD / SUB into load / store (to form pre-indexed, post-indexed
load / store) if the ADD / SUB has a live definition of CPSR.

Bug reported by David Meyer. Alas, no test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149970 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-07 07:09:28 +00:00
dbd98a4b1b Add instruction selection for 256-bit VPSHUFD and 128-bit VPERMILPS/VPERMILPD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149968 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-07 06:28:42 +00:00
bc2198133a Convert assert(0) to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-07 02:50:20 +00:00
3901c3e750 [fast-isel] Add support for ADDs with non-legal types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149934 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-06 23:50:07 +00:00
6939fde29c Add TargetPassConfig to the PassManager for use inside passes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149926 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-06 22:51:15 +00:00
2ea93875b2 Enable streaming of bitcode
This CL delays reading of function bodies from initial parse until
materialization, allowing overlap of compilation with bitcode download.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149918 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-06 22:30:29 +00:00
7302d80490 Remove some dead code and tidy things up now that vectors use ConstantDataVector
instead of always using ConstantVector.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149912 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-06 21:56:39 +00:00
aa5abe88d6 [unwind removal] We no longer have 'unwind' instructions being generated, so
remove the code that handles them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149901 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-06 21:16:41 +00:00
699ddcbcb3 X86: Don't call malloc for 4 bits. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149866 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-06 12:06:18 +00:00
f3fd7ee415 Hexagon: Remove forbidden iostream includes (it introduces static initializers)
Reorder includes while at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149863 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-06 10:19:29 +00:00
d156dc11f9 Add shuffle decoding support for 256-bit pshufd. Merge vpermilp* and pshufd decoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149859 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-06 07:17:51 +00:00
dc7c716a1c DefinesPredicate should only look for def operands. Patch by Ludwig Meier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149846 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 19:55:04 +00:00
23f612113a Remove dead test: this was already checked and handled a few lines
above.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149841 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 19:30:06 +00:00
5b8a1db7ea Persuade GCC that there is nothing worth warning about here (there isn't).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149834 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 14:20:11 +00:00
853066a32a Don't initialize CV in terms of itself! Spotted by GCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149833 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 14:16:09 +00:00
69f44692bf Begin fleshing out more convenience predicates in llvm::Triple and
convert at least one client over to use them. Subsequent patches both to
LLVM and Clang will try to convert more people over to a common set of
predicates.

This round of predicates is focused on OS-categorization predicates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149815 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 08:26:40 +00:00
655b8de7b2 Convert assert(0) to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 07:21:30 +00:00
6d1263acb9 Convert assert(0) to llvm_unreachable in X86 Target directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149809 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 05:38:58 +00:00
abb94d0687 Convert some assert(0) in default of switch statements to llvm_unreachable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149808 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 03:43:23 +00:00
5b209e84f4 Add target specific node for PMULUDQ. Change patterns to use it and custom lower intrinsics to it. Use it instead of intrinsic to handle 64-bit vector multiplies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149807 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 03:14:49 +00:00
18c7f80b3e reapply the patches reverted in r149470 that reenable ConstantDataArray,
but with a critical fix to the SelectionDAG code that optimizes copies
from strings into immediate stores: the previous code was stopping reading
string data at the first nul.  Address this by adding a new argument to
llvm::getConstantStringInfo, preserving the behavior before the patch.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149800 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 02:29:43 +00:00
eea723fe02 Remove most of the intrinsics for XOP VPCMOV instruction. They all aliased to the same instruction with different types. This would be better accomplished with casts in the not yet created xopintrin.h header file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149795 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 00:55:56 +00:00
061efcfb3e TargetPassConfig: confine the MC configuration to TargetMachine.
Passes prior to instructon selection are now split into separate configurable stages.
Header dependencies are simplified.
The bulk of this diff is simply removal of the silly DisableVerify flags.

Sorry for the target header churn. Attempting to stabilize them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149754 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-04 02:56:59 +00:00
769422f0fc [fast-isel] Add support for URem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149716 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 21:23:45 +00:00
ae46a3362d [fast-isel] Rename isZExt to isSigned. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149714 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 21:14:11 +00:00
7ccb30b596 [fast-isel] Add support for UDIV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 21:07:27 +00:00
ee8901c08f [fast-isel] Add support for FPToUI. Also add test cases for FPToSI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149706 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 20:27:51 +00:00
36b7beb429 [fast-isel] Add support for selecting UIToFP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149704 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 19:42:52 +00:00
a02556679e Remove getShuffleVPERMILPImmediate function, getShuffleSHUFImmediate performs the same calculation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149683 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 06:52:33 +00:00
fa5b70e1d8 Remove unnecessary qualification on 256-bit vector handling in LowerBUILD_VECTOR. Condition was already guaranteed by earlier code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149680 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 06:32:21 +00:00
843ee2e6a4 Added TargetPassConfig. The first little step toward configuring codegen passes.
Allows command line overrides to be centralized in LLVMTargetMachine.cpp.
LLVMTargetMachine can intercept common passes and give precedence to command line overrides.
Allows adding "internal" target configuration options without touching TargetOptions.
Encapsulates the PassManager.
Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs.
Allows modifying the target configuration hooks without rebuilding the world.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149672 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-03 05:12:41 +00:00