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942827b113
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26479 Commits

Author SHA1 Message Date
Chad Rosier
942827b113 [AArch64] Add support for NEON scalar integer compare instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192596 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-14 14:37:20 +00:00
Bernard Ogden
0d1e2aebe6 Add Cortex-A57 support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192591 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-14 13:17:07 +00:00
Bernard Ogden
7220572e74 Add subtarget feature support for Cortex-A53 
Some previous implicit defaults have changed, for example FP and NEON
are now on by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192590 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-14 13:16:57 +00:00
Matheus Almeida
9672a89c71 [mips][msa] Direct Object Emission support for BIT instructions. 
List of instructions:
bclri.{b,h,w,d}
binsli.{b,h,w,d}
binsri.{b,h,w,d}
bnegi.{b,h,w,d}
bseti.{b,h,w,d}
sat_s.{b,h,w,d}
sat_u.{b,h,w,d}
slli.{b,h,w,d}
srai.{b,h,w,d}
srari.{b,h,w,d}
srli.{b,h,w,d}
srlri.{b,h,w,d}



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192589 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-14 13:07:39 +00:00
Matheus Almeida
e89c50acc8 [mips][msa] Direct Object Emission support for VEC instructions. 
List of instructions:
and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192588 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-14 12:57:18 +00:00
Matheus Almeida
01436ba306 [mips][msa] Direct Object Emission of INSVE.{b,h,w,d}. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192587 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-14 12:38:17 +00:00
Matheus Almeida
29adbe8464 [mips][msa] Direct Object Emission for the majority of the ELM instructions. 
List of instructions:
copy_s.{b,h,w}
copy_u.{b,h,w}
sldi.{b,h,w,d}
splati.{b,h,w,d}



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192586 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-14 12:22:43 +00:00
Matheus Almeida
45ecbfc8e5 [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction. 
INSERT is the first type of MSA instruction that requires a change to the way
MSA registers are parsed. This happens because MSA registers may be suffixed by
an index in the form of an immediate or a general purpose register. The changes
to parseMSARegs reflect that requirement.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192582 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-14 11:49:30 +00:00
Elena Demikhovsky
55240a5ddb Fixed a bug in dynamic allocation memory on stack. 
The alignment of allocated space was wrong, see Bugzila 17345.

Done by Zvi Rackover <zvi.rackover@intel.com>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192573 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-14 07:26:51 +00:00
Craig Topper
f50045e90d Create classes to reduce the size of the tablegen entries for the CRC32 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192568 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-14 05:19:58 +00:00
Craig Topper
c6f7c99809 Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192567 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-14 04:55:01 +00:00
Craig Topper
8e121843c1 Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192566 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-14 01:42:32 +00:00
Craig Topper
bae9f69d37 Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the disassembler tables. Add PINSRWrr64i to complement the AVX version. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192565 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-14 01:21:22 +00:00
Craig Topper
eefca96792 Don't use 64-bit versions of MOVMSKPD in CodeGen. The instructions only produce a 1-bit result so we can just use SUBREG_TO_REG to extend the 32-bit versions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192562 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-14 00:24:33 +00:00
Vincent Lejeune
cf1f4c7dd1 R600: improve dump of S_WAITCNT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192557 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-13 17:56:28 +00:00
Vincent Lejeune
36d96337f7 R600/SI: Add SinkingPass before ISel 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192556 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-13 17:56:21 +00:00
Vincent Lejeune
6a809a8d29 R600/SI: Support byval arguments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192555 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-13 17:56:16 +00:00
Vincent Lejeune
f2b3a569ae R600: Use masked read sel for texture instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192554 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-13 17:56:10 +00:00
Vincent Lejeune
91ec4b0cac R600: fix swizzle export 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192553 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-13 17:56:04 +00:00
Vincent Lejeune
6639f066e1 R600: Clear the VPM bit of export instructions. 
It makes apparently no change it to set this bit or not but the
docs recommand to left it cleared.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192552 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-13 17:55:57 +00:00
Craig Topper
017d8a3e23 Remove more filters from the disassembler. Mark some AVX512 instructions as CodeGenOnly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192525 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-12 05:41:08 +00:00
Tom Stellard
f931867317 R600: Store disassembly in a special ELF section when feature +DumpCode is enabled. 
Patch by: Jay Cornwall

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192523 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-12 05:02:51 +00:00
Craig Topper
c429b5cca1 Mark some more instructions as CodeGenOnly. Remove filters from the disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192522 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-12 04:46:18 +00:00
Reed Kotler
7f0125ba19 For Mips16, start to consolidate all forms of 32 bit literal loading so that 
they can be better handled and optimized in the Mips16 constant island code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192520 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-12 02:19:08 +00:00
Will Dietz
e3ba15c794 Add missing #include's to cctype when using isdigit/alpha/etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192519 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-12 00:55:57 +00:00
Matt Arsenault
e1bd218334 Fix typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192499 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 21:03:36 +00:00
Benjamin Kramer
5af763cb2a Mips: Disassemble sign-extended 64 bit immediates properly. 
This doesn't change the meaning of the output, but makes look right. PR17539.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192483 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 19:05:08 +00:00
Amara Emerson
fc3dc102e0 [ARM] Fix FP ABI attributes with no VFP enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192458 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 16:03:43 +00:00
Matheus Almeida
21d60f02c3 This reverts 192447 because of compiler warning generated on darwin build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192451 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 13:58:32 +00:00
Matheus Almeida
abba71663e This reverts r192449 because of compiler warning generated on darwin build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192450 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 13:56:12 +00:00
Matheus Almeida
62a69eee5a [mips][msa] Direct Object Emission for the majority of the ELM instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192449 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 13:39:49 +00:00
Matheus Almeida
6f36ea5c47 [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction. 
INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. 
This happens because MSA registers may be suffixed by an index in the form of an immediate or a
 general purpose register. The changes to parseMSARegs reflect that requirement.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192447 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 13:29:36 +00:00
Justin Holewinski
81d9902bb1 [NVPTX] Switch from StrongPHIElimination to PHIElimination in NVPTXTargetMachine, and add some missing optimization passes to addOptimizedRegAlloc 
Fixes PR17529

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192445 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 12:39:39 +00:00
Justin Holewinski
43777c3150 Make AsmPrinter::emitImplicitDef a virtual method so targets can emit custom comments for implicit defs 
For NVPTX, this fixes a crash where the emitImplicitDef implementation was expecting physical registers,
while NVPTX uses virtual registers (with a couple of exceptions).  Now, the implicit def comment will be
emitted as a true PTX register name. Other targets can use this to customize the output of implicit def
comments.

Fixes PR17519

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192444 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 12:39:36 +00:00
Daniel Sanders
a6e253ddd0 [mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from normal IR (i.e. not intrinsics) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192438 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 10:50:42 +00:00
Daniel Sanders
4fa2c32220 [mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not intrinsics) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192435 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 10:27:32 +00:00
Robert Lytton
ed0ed946ab XCore target fix bug in emitArrayBound() causing segmentation fault 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192434 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 10:27:13 +00:00
Robert Lytton
4315b2b504 XCore target does not emit '.hidden' or '.protected' attributes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192433 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 10:27:00 +00:00
Robert Lytton
fb312f9f5a XCore target: fix bug in XCoreLowerThreadLocal.cpp 
When a ConstantExpr which uses a thread local is part of a PHI node
instruction, the insruction that replaces the ConstantExpr must
be inserted in the predecessor block, in front of the terminator instruction.
If the predecessor block has multiple successors, the edge is first split.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192432 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 10:26:48 +00:00
Robert Lytton
7b5376659c XCore target: add XCoreTargetLowering::isZExtFree() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192431 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 10:26:29 +00:00
Daniel Sanders
c879eabcc2 [mips][msa] Added support for matching fmadd.[wd] from normal IR (i.e. not intrinsics) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192430 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 10:14:25 +00:00
Daniel Sanders
b9bee10b21 [mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] from normal IR (i.e. not intrinsics) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192429 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 10:00:06 +00:00
Kevin Qin
767f816b92 Implement aarch64 neon instruction set AdvSIMD (copy). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192410 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 02:33:55 +00:00
Matt Arsenault
6c066c044e Fix typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192406 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 23:05:37 +00:00
Matt Arsenault
1cc41bf63c R600: Fix trunc i64 to i32 on SI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192375 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 18:04:16 +00:00
Tom Stellard
47fbbc2dc5 R600/SI: Implement SIInstrInfo::verifyInstruction() for VOP* 
The function is used by the machine verifier and checks that VOP*
instructions have legal operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192367 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 17:11:55 +00:00
Tom Stellard
0f9eaaa8aa R600/SI: Define a separate MIMG instruction for each possible output value type 
During instruction selection, we rewrite the destination register
class for MIMG instructions based on their writemasks.  This creates
machine verifier errors since the new register class does not match
the register class in the MIMG instruction definition.

We can avoid this by defining different MIMG instructions for each
possible destination type and then switching to the correct instruction
when we change the register class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192365 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 17:11:24 +00:00
Tom Stellard
219e788dc6 R600/SI: Mark the EXEC register as reserved 
This prevents the machine verifier from complaining about uses of
an undefined physical register.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192364 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 17:11:19 +00:00
Tom Stellard
de28bdadff R600: Use StructurizeCFGPass for non SI targets 
StructurizeCFG pass allows to make complex cfg reducible ; it allows a lot of
shader from shadertoy (which exhibits complex control flow constructs) to works
correctly with respect to CFG handling (and allow us to detect potential bug in
other part of the backend).

We provide a cmd line argument to disable the pass for debug purpose.

Patch by: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192363 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 17:11:12 +00:00
Hao Liu
6a5a667517 Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). 
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192361 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 17:00:52 +00:00