Commit Graph

87798 Commits

Author SHA1 Message Date
Akira Hatanaka
9bf571fe2c [mips] Refactor SLT (set on less than) instructions. Separate encoding
information from the rest. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 04:27:52 +00:00
Akira Hatanaka
c23061547d [mips] Refactor unconditional branch instruction. Separate encoding information
from the rest. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170663 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 04:22:39 +00:00
Akira Hatanaka
1e7739f614 [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass
parameter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170661 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 04:20:09 +00:00
Akira Hatanaka
77e85f367c [mips] Delete definition of CPRESTORE instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170660 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 04:15:30 +00:00
Akira Hatanaka
5c54025645 [mips] Refactor conditional branch instructions with one register operand.
Separate encoding information from the rest.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170659 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 04:13:23 +00:00
Richard Smith
488fdce982 Don't use isa<CallInst>(this) in the constructor for CallInst's base class.
This has undefined behavior, because the classof implementation attempts to
access parts of the not-yet-constructed derived class. Found by clang
-fsanitize=vptr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170658 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 04:11:02 +00:00
Akira Hatanaka
c488901355 [mips] Refactor conditional branch instructions with two register operands.
Separate encoding information from the rest.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170657 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 04:10:13 +00:00
Reed Kotler
cef95f702a fix most of remaining issues with large frames.
these patches are tested a lot by test-suite but
make check tests are forthcoming once the next
few patches that complete this are committed.
with the next few patches the pass rate for mips16 is
near 100%



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170656 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 04:07:42 +00:00
Akira Hatanaka
68fe665b9a [mips] Use "or $r0, $r1, $zero" instead of "addu $r0, $zero, $r1" to copy
physical register $r1 to $r0.

GNU disassembler recognizes an "or" instruction as a "move", and this change
makes the disassembled code easier to read.

Original patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 04:06:06 +00:00
Richard Smith
ba836a2e80 Fix use-before-construction of X86TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170654 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 04:04:17 +00:00
Richard Smith
fe4ef2c2ae Don't use -1 as a value of an unsigned 7-bit enumeration; that has undefined
behavior and violates the !range constraints we put on loads of this enum.
Found by clang -fsanitize=enum.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170653 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 04:02:58 +00:00
Richard Smith
e8ce626308 Don't leave IsUnsigned uninitialized in a default-constructed APSInt. Copying
such a structure has undefined behavior. Caught by -fsanitize=bool.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170652 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 03:59:24 +00:00
Akira Hatanaka
2427773f2f [mips] Change the order of template parameters. Move the default parameters to
the end. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170651 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 03:52:08 +00:00
Akira Hatanaka
cdc0c59d1e [mips] Refactor shift instructions with register operands. Separate encoding
information from the rest.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170650 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 03:48:24 +00:00
Akira Hatanaka
0dad34a9bf [mips] Refactor shift immediate instructions. Separate encoding information
from the rest.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170649 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 03:44:41 +00:00
Akira Hatanaka
ab48c503e2 [mips] Refactor arithmetic and logic instructions with immediate operands.
Separate encoding information from the rest.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170648 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 03:40:03 +00:00
Akira Hatanaka
23a3da0113 [mips] Refactor arithmetic and logic instructions. Separate encoding
information from the rest.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170647 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 03:34:05 +00:00
Sean Silva
7d31849c44 docs: Show TOC for GettingStarted.rst.
This is a pretty lengthy document, so put the table of contents in your
face so that it's easier to scope out the content.

This document is a mess currently and needs to be
refactored/revised/split-up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 03:32:39 +00:00
Akira Hatanaka
c9e30ea42c [mips] Delete ArithOverflowR and ArithOverflow and use ArithLogicR and
ArithLogicI as the instruction base classes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170642 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 03:00:16 +00:00
Sean Silva
6241703ee4 docs: Clean up adornments.
For whatever reason the usage of '^^^' and '---' adornments were
reversed compared to the "canonical" style of the LLVM docs (which is
currently "the style used in SphinxQuickstartTemplate.rst"). This change
doesn't affect the document structure at all, I'm just doing it for
trivial stylistic consistency (the document content is *much* more
important---thanks Nadav for writing this up!).

Also, trim the adornments to be the same length as the section names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170638 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 02:40:45 +00:00
Sean Silva
68d5b27b36 docs: ASCII-fy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170637 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 02:23:25 +00:00
Nadav Rotem
d3071bb042 Loop Vectorizer: Enable if-conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170632 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 02:00:02 +00:00
Bill Wendling
f6670729aa s/AttributesImpl/AttributeImpl/g This is going to apply to Attribute, not Attributes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170631 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 01:36:59 +00:00
Bob Wilson
99d8e76d44 Do not introduce vector operations in functions marked with noimplicitfloat.
<rdar://problem/12879313>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170630 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 01:36:20 +00:00
Jim Grosbach
46367768f7 Clean up some DOxygen comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170629 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 01:14:48 +00:00
Jim Grosbach
39758cd55d Clean up some DOxygen comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170628 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 01:14:45 +00:00
Richard Smith
8efd0f00be Fix an uninitialized member variable, found by -fsanitize=bool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170627 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 01:05:39 +00:00
Nadav Rotem
a6603b35a9 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170626 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 00:49:56 +00:00
Nadav Rotem
f9962d9391 doc: resize the image.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170622 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 00:29:18 +00:00
NAKAMURA Takumi
6b207d3cfa Target/R600: Update MIB according to r170588.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170620 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 00:22:11 +00:00
Nadav Rotem
6d1fc5389f Doc: update the chart.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170618 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 00:03:36 +00:00
Bill Wendling
5f93e2bee5 Add a context so that once we uniquify strings we can access them easily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170615 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 23:55:43 +00:00
Jim Grosbach
fbf3b4a076 MC: Add MCInstrDesc::mayAffectControlFlow() method.
MC disassembler clients (LLDB) are interested in querying if an
instruction may affect control flow other than by virtue of being
an explicit branch instruction. For example, instructions which
write directly to the PC on some architectures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170610 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 23:38:53 +00:00
Jim Grosbach
16f3204b95 Add isSubRegisterEq() and isSuperRegisterEq().
isSub and isSuper return false if RegA == RegB. Add variants which also
include the identity function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170609 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 23:38:49 +00:00
Jim Grosbach
e188fb7dd9 Move isSubRegister() and isSuperRegister to MCRegisterInfo.
These were defined on TargetRegisterInfo, but they don't use any information
that's not available in MCRegisterInfo, so sink them down to be available
at the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170608 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 23:38:46 +00:00
Jim Grosbach
dd2fa5195e Fix doc comment. '///' not '//'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170607 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 23:38:44 +00:00
Michael Ilseman
f846f16c92 Refactor isIntrinsic() to be quicker, and change classof() (and thus, isa<IntrinsicInst>()) to use it. This decreases the number of occurrences of the slow-path string matching performed by getIntrinsicID().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170602 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 23:17:20 +00:00
Bill Wendling
18e7211068 s/AttributeListImpl/AttributeSetImpl/g to match the namechange of AttributeList.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170600 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 22:42:22 +00:00
Jakob Stoklund Olesen
7f4bb1b9f0 Always use addOperand(MF, MO) from MachineInstrBuilder.
The single-argument MachineInstr::addOperand(MO) will be removed soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170599 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 22:35:46 +00:00
Dmitri Gribenko
344df79cc0 Add a missing 'else'. Found by grep '} if'
No testcase because it is apparently not so trivial to construct.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170595 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 22:13:01 +00:00
Tom Stellard
afb71e4271 R600: Add entry in CODE_OWNERS.TXT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170594 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 22:10:35 +00:00
Tom Stellard
45f75be564 R600: Remove unecessary VREG alignment.
Unlike SGPRs VGPRs doesn't need to be aligned.

Patch by: Christian König

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170593 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 22:10:34 +00:00
Tom Stellard
d09d43ae53 R600: control flow optimization
Branch if we have enough instructions so that it makes sense.
Also remove branches if they don't make sense.

Patch by: Christian König

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170592 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 22:10:33 +00:00
Tom Stellard
6b7d99d473 R600: New control flow for SI v2
This patch replaces the control flow handling with a new
pass which structurize the graph before transforming it to
machine instruction. This has a couple of different advantages
and currently fixes 20 piglit tests without a single regression.

It is now a general purpose transformation that could be not
only be used for SI/R6xx, but also for other hardware
implementations that use a form of structurized control flow.

v2: further cleanup, fixes and documentation

Patch by: Christian König

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170591 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 22:10:31 +00:00
Eric Christopher
6eebe47060 Split out abbreviations for the skeleton info from the rest of
the abbreviations. Part of implementing split dwarf.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170589 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 22:02:53 +00:00
Jakob Stoklund Olesen
37a942cd52 Remove the explicit MachineInstrBuilder(MI) constructor.
Use the version that also takes an MF reference instead.

It would technically be possible to extract an MF reference from the MI
as MI->getParent()->getParent(), but that would not work for MIs that
are not inserted into any basic block.

Given the reasonably small number of places this constructor was used at
all, I preferred the compile time check to a run time assertion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170588 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 21:31:56 +00:00
Nadav Rotem
521396ab37 Fix a bug that was found by building clang with -fsanitize.
I introduced it in r166785. PR14291.

If TD is unavailable use getScalarSizeInBits, but don't optimize
pointers or vectors of pointers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170586 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 20:47:04 +00:00
Meador Inge
83ccac71ff docs: Fix title underline warnings
Building Vectorizers.rst produces a few warnings of the form:

   WARNING: Title underline too short.

Fixed by adding the extra needed dashes under the title.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170582 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 20:16:40 +00:00
Evan Cheng
733c6b1db1 LLVM sdisel normalize bit extraction of the form:
((x & 0xff00) >> 8) << 2
to
 (x >> 6) & 0x3fc

This is general goodness since it folds a left shift into the mask. However,
the trailing zeros in the mask prevents the ARM backend from using the bit
extraction instructions. And worse since the mask materialization may require
an addition instruction. This comes up fairly frequently when the result of 
the bit twiddling is used as memory address. e.g.

 = ptr[(x & 0xFF0000) >> 16]

We want to generate:
  ubfx   r3, r1, #16, #8
  ldr.w  r3, [r0, r3, lsl #2]

vs.
  mov.w  r9, #1020
  and.w  r2, r9, r1, lsr #14
  ldr    r2, [r0, r2]

Add a late ARM specific isel optimization to
ARMDAGToDAGISel::PreprocessISelDAG(). It folds the left shift to the
'base + offset' address computation; change the mask to one which doesn't have
trailing zeros and enable the use of ubfx.

Note the optimization has to be done late since it's target specific and we
don't want to change the DAG normalization. It's also fairly restrictive
as shifter operands are not always free. It's only done for lsh 1 / 2. It's
known to be free on some cpus and they are most common for address
computation.

This is a slight win for blowfish, rijndael, etc.

rdar://12870177


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170581 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 20:16:09 +00:00
Benjamin Kramer
28d24c95ad Remove edis remnant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170580 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19 20:11:17 +00:00