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1963 Commits

Author SHA1 Message Date
Evan Cheng
d3e18fad7e These are done / no longer care. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85798 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 07:58:25 +00:00
Evan Cheng
e3b88fc01e Add an entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85797 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 07:51:19 +00:00
Evan Cheng
7baae87d8f Unbreak ARMBaseRegisterInfo::copyRegToReg. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85787 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 04:44:55 +00:00
Anton Korobeynikov
2ae0eec1c0 Handle splats of undefs properly. This includes the testcase for PR5364 as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85767 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 00:12:06 +00:00
Anton Korobeynikov
3a639a07ea Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364. 
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85766 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 00:11:39 +00:00
Anton Korobeynikov
2e1da9fea4 64-bit FP loads & stores operate on both NEON and VFP pipelines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85765 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 00:11:06 +00:00
Anton Korobeynikov
f95215f551 Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85764 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-02 00:10:38 +00:00
Evan Cheng
e3ce8aab0a Fix a couple more places where we are creating ld / st instructions without memoperands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85746 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-01 22:04:35 +00:00
Evan Cheng
48d8afab73 Make use of imm12 version of Thumb2 ldr / str instructions more aggressively. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85743 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-01 21:12:51 +00:00
Evan Cheng
de17fb6e4d Use cbz and cbnz instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85698 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 23:46:45 +00:00
Jim Grosbach
8cd0a8cb82 vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using 
them for scalar floating point operations for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85697 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 22:57:36 +00:00
Jim Grosbach
bcf2f2c159 Expand 64-bit logical shift right inline 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85687 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 21:42:19 +00:00
Jim Grosbach
b4a976c304 Expand 64-bit arithmetic shift right inline 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85685 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 21:00:56 +00:00
Jim Grosbach
c2b879fcfe Expand 64 bit left shift inline rather than using the libcall. For now, this 
is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85675 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 19:38:01 +00:00
Evan Cheng
9eda68988e It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85643 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-31 03:39:36 +00:00
Kevin Enderby
9c41fa87ea Updates to the ARM target assembler for llvm-mc per review comments from 
Daniel Dunbar.
- Reordered the fields in the ARMOperand Mem struct to make the struct smaller.
Making bool's into 1 bit fields and put the MCExpr* fields adjacent to each
other.
- Fixed a number of places in ARMAsmParser.cpp so they have doxygen comments.
- Change the name of ARMAsmParser::ParseRegister() to MaybeParseRegister and
added the bool ParseWriteBack parameter.
- Changed ARMAsmParser::ParseMemory() to call MaybeParseRegister().
- Added ARMAsmParser::ParseMemoryOffsetReg to factor out parsing the offset of a
memory operand.  And use it for both parsing both preindexed and post indexing
addressing forms in ARMAsmParser::ParseMemory.
- Changed the first argument to ParseShift() to a reference.
- Changed ParseShift() to check for Rrx first and return to reduce nesting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85632 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 22:55:57 +00:00
Bob Wilson
57f224a5a4 Add a note about Robert Muth's alternate jump table implementation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85624 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 22:22:46 +00:00
Bob Wilson
929ffa2414 Fix a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85610 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 20:13:25 +00:00
Rafael Espindola
c1382b745f This fixes functions like 
void f (int a1, int a2, int a3, int a4, int a5,...)

In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85590 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 14:33:14 +00:00
Bob Wilson
ddb16df912 Add ARM codegen for indirect branches. 
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85577 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 05:45:42 +00:00
Jim Grosbach
95d9504d46 Dial back the realignment a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85546 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-30 00:08:40 +00:00
Dan Gohman
533297b58d Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-29 18:10:34 +00:00
Jim Grosbach
84e58d03c9 To get more thorough testing from llc-beta nightly runs, do dynamic stack 
realignment regardless of whether it's strictly necessary.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85476 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-29 02:41:21 +00:00
Bob Wilson
a597103c32 Revert r85346 change to control tail merging by CodeGenOpt::Level. 
I'm going to redo this using the OptimizeForSize function attribute.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85426 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 20:46:46 +00:00
Bob Wilson
8d4de5abfa Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the 
opcode and operand with a tab.  Check for these instructions in the usual
places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85411 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 18:26:41 +00:00
Evan Cheng
30c80211b6 fconsts and fconstd are obviously re-materializable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85410 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 18:19:56 +00:00
Jim Grosbach
ca5dfb71ba Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85406 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 17:33:28 +00:00
Evan Cheng
c59420867e Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85381 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 06:55:03 +00:00
Evan Cheng
39382427f1 Use fconsts and fconstd to materialize small fp constants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85362 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 01:44:26 +00:00
Bob Wilson
04ea6e5150 Add an indirect branch pattern for ARM. Testcase will be coming soon. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85355 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-28 00:37:03 +00:00
Bob Wilson
cd4f04d6bc Record CodeGen optimization level in the BranchFolding pass so that we can 
use it to control tail merging when there is a tradeoff between performance
and code size.  When there is only 1 instruction in the common tail, we have
been merging.  That can be good for code size but is a definite loss for
performance.  Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3".  Radar 7338114.

Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level.  Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor.  If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85346 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 23:49:38 +00:00
Jim Grosbach
a6a99b4e16 Enable virtual register based frame index scavenging by default for ARM & T2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85335 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 22:52:29 +00:00
Jim Grosbach
3dab277857 Infrastructure for dynamic stack realignment on ARM. For now, this is off by 
default behind a command line option. This will enable better performance for
vectors on NEON enabled processors.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85333 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 22:45:39 +00:00
Johnny Chen
90d7dcfdd9 Similar to r85280, do not clear the "S" bit for RSBri and RSBrs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85299 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 20:51:49 +00:00
Johnny Chen
eadeffb306 Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between 
BL_pred and BLr9_pred.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85297 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 20:45:15 +00:00
Bob Wilson
f3b0d1a555 Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI" 
instruction format that already takes care of setting this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85280 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 19:52:03 +00:00
Johnny Chen
76b39e88e4 Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10}) 
for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85271 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 18:44:24 +00:00
Johnny Chen
6a3b5eec89 Test commit. Added '.' to the comment line. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85255 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 17:25:15 +00:00
Rafael Espindola
f87611272b Correctly align double arguments in the stack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85235 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 14:09:44 +00:00
Evan Cheng
dd22a45acc Now VFP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85186 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 00:20:49 +00:00
Evan Cheng
699bebac4f Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85184 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 00:08:59 +00:00
Evan Cheng
162e30921d Change ARM asm strings to separate opcode from operands with a tab instead of a space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85178 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 23:45:59 +00:00
Bob Wilson
dda9583e51 Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding 
bits.  Johnny, please review -- I do not have a good track record of getting
these right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85173 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 22:59:12 +00:00
Bob Wilson
d9ecd3108f Fix ARM encoding typo: Opcod3 is not passed to ASuI parent class. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85169 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 22:42:13 +00:00
Bob Wilson
7e053bb33c Add more ARM instruction encodings for 's' bit set and "rs" register encoding 
bits.  Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85167 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 22:34:44 +00:00
David Goodwin
2e7be612d5 Break anti-dependence breaking out into its own class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85127 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 16:59:04 +00:00
Jim Grosbach
dd5694203b of -> or 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85065 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 19:14:48 +00:00
Jim Grosbach
f639e9f9e6 80-column cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85064 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 18:55:46 +00:00
Evan Cheng
4f54c1293a Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85049 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 07:53:28 +00:00
Evan Cheng
ed3ad212ec Don't forget subreg indices when folding load / store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85048 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 07:52:27 +00:00