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1390 Commits

Author SHA1 Message Date
Evan Cheng
b00dddd164 Match more post-indexed ops. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31569 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-08 20:27:27 +00:00
Jim Laskey
d6c3422e31 Remove redundant <cmath>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31561 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-08 19:16:44 +00:00
Evan Cheng
03fa6ea402 - When performing pre-/post- indexed load/store transformation, do not worry 
about whether the new base ptr would be live below the load/store. Let two
  address pass split it back to non-indexed ops.
- Minor tweaks / fixes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31544 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-08 08:30:28 +00:00
Evan Cheng
a4f53ef527 Fixed a minor bug preventing some pre-indexed load / store transformation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31543 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-08 06:56:05 +00:00
Reid Spencer
3822ff5c71 For PR950: 
This patch converts the old SHR instruction into two instructions,
AShr (Arithmetic) and LShr (Logical). The Shr instructions now are not
dependent on the sign of their operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31542 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-08 06:47:33 +00:00
Evan Cheng
6c1491dd06 Fix a obscure post-indexed load / store dag combine bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31537 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-08 02:38:55 +00:00
Evan Cheng
bbd6f6ec1a Add post-indexed load / store transformations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31498 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-07 09:03:05 +00:00
Chris Lattner
fa9aa2b424 Fix PR988 and CodeGen/Generic/2006-11-06-MemIntrinsicExpand.ll. 
The low part goes in the first operand of expandop, not the second one.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31487 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-07 04:11:44 +00:00
Evan Cheng
d5ad440f43 Remove dead code; added a missing null ptr check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31478 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-06 21:33:46 +00:00
Evan Cheng
3ef554d2b1 Add comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31473 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-06 08:14:30 +00:00
Jeff Cohen
d41b30def3 Unbreak VC++ build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31464 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-05 19:31:28 +00:00
Evan Cheng
33dbedcdcb Added pre-indexed store support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31459 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-05 09:31:14 +00:00
Evan Cheng
9109fb1eb7 Added getIndexedStore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31458 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-05 09:30:09 +00:00
Evan Cheng
95f6edeff5 Changes to use operand constraints to process two-address instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31453 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-04 09:44:31 +00:00
Evan Cheng
e6e97e66a3 Fix comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31414 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 07:31:32 +00:00
Evan Cheng
1a854be352 Rename 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31413 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 07:21:16 +00:00
Reid Spencer
b8f4e0aa17 Remove dead variable. Fix 80 column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31412 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 03:30:34 +00:00
Evan Cheng
7fc033a24d Added DAG combiner transformation to generate pre-indexed loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31410 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 03:06:21 +00:00
Evan Cheng
c5fc57dcae Added isPredecessor. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31409 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 03:05:24 +00:00
Chris Lattner
02cb49ee67 silence warning 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31397 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-03 01:28:29 +00:00
Reid Spencer
3ed469ccd7 For PR786: 
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31380 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-02 20:25:50 +00:00
Reid Spencer
0a783f783c For PR950: 
Replace the REM instruction with UREM, SREM and FREM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31369 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-02 01:53:59 +00:00
Chris Lattner
2a821601f1 Allow the getRegForInlineAsmConstraint method to return a register class with 
no fixes physreg.  Treat this as permission to use any register in the register
class.  When this happens and it is safe, allow the llvm register allcoator to
allocate the register instead of doing it at isel time.  This eliminates a ton
of copies around common inline asms.  For example:

int test2(int Y, int X) {
  asm("foo %0, %1" : "=r"(X): "r"(X));
  return X;
}

now compiles to:

_test2:
        foo r3, r4
        blr

instead of:

_test2:
        mr r2, r4
        foo r2, r2
        mr r3, r2
        blr

GCC produces:

_test2:
        foo r4, r4
        mr r3,r4
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31366 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-02 01:41:49 +00:00
Evan Cheng
1dabb68ab4 Clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31359 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-01 22:39:30 +00:00
Evan Cheng
93467e7fe3 CopyFromReg starts a live range so its use should not be considered a floater. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31356 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-01 22:17:06 +00:00
Evan Cheng
6cc31ae4da Print jumptable index. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31340 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-11-01 04:48:30 +00:00
Chris Lattner
0ccb500fa7 Compile CodeGen/PowerPC/fp-branch.ll to: 
_intcoord_cond_next55:
LBB1_3: ;cond_next55
        lis r2, ha16(LCPI1_0)
        lfs f0, lo16(LCPI1_0)(r2)
        fcmpu cr0, f1, f0
        blt cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
        li r3, 1
        blr
LBB1_2: ;cond_next62.exitStub
        li r3, 0
        blr

instead of:

_intcoord_cond_next55:
LBB1_3: ;cond_next55
        lis r2, ha16(LCPI1_0)
        lfs f0, lo16(LCPI1_0)(r2)
        fcmpu cr0, f1, f0
        bge cr0, LBB1_1 ;bb72.exitStub
LBB1_4: ;cond_next55
        lis r2, ha16(LCPI1_0)
        lfs f0, lo16(LCPI1_0)(r2)
        fcmpu cr0, f1, f0
        bnu cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
        li r3, 1
        blr
LBB1_2: ;cond_next62.exitStub
        li r3, 0
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31330 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-31 23:06:00 +00:00
Chris Lattner
df19f27d03 look through isunordered to inline it into branch blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31328 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-31 22:37:42 +00:00
Chris Lattner
efa46ce87b handle global address constant sdnodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31323 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-31 20:01:56 +00:00
Chris Lattner
53069fbbae TargetLowering::isOperandValidForConstraint 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31319 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-31 19:41:18 +00:00
Chris Lattner
dba1aeedd8 Change the prototype for TargetLowering::isOperandValidForConstraint 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31318 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-31 19:40:43 +00:00
Chris Lattner
d03f1581c8 Turn an assert into an error message. This is commonly triggered when 
we don't support a specific constraint yet.  When this happens, print the
unsupported constraint.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31310 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-31 07:33:13 +00:00
Evan Cheng
d063189c09 Fix a typo which can break jumptables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31305 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-31 02:31:00 +00:00
Evan Cheng
3d4ce11085 Lower jumptable to BR_JT. The legalizer can lower it to a BRIND or let the target custom lower it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31293 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-30 08:00:44 +00:00
Evan Cheng
c41cd9c391 Added a new SDNode type: BR_JT for jumptable branch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31292 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-30 07:59:36 +00:00
Chris Lattner
6a586c8d9a fix Generic/2006-10-29-Crash.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31281 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-29 21:01:20 +00:00
Chris Lattner
5a145f0094 Fix a load folding issue that Evan noticed: there is no need to export values 
used by comparisons in the main block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31279 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-29 18:23:37 +00:00
Evan Cheng
ba726ab3ec VLOAD is not the LoadSDNode opcode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31276 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-29 06:14:47 +00:00
Nick Lewycky
f6aaaaa39e Remove spurious case. EXTLOAD is not one of the node opcodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31275 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-29 02:26:30 +00:00
Chris Lattner
bad7f48c70 split critical edges more carefully and intelligently. In particular, critical 
edges whose destinations are not phi nodes don't bother us.  Also, share
split edges, since the split edge can't have a phi.  This significantly
reduces the complexity of generated code in some cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31274 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-28 19:22:10 +00:00
Jim Laskey
1c6f01aaa5 Load and stores have not been uniqued properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31261 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-28 17:25:28 +00:00
Chris Lattner
47e32e6b83 Split *all* critical edges before isel. This resolves issues with spill code 
being inserted on unsplit critical edges, which introduces (sometimes large
amounts of) partially dead spill code.

This also fixes PR925 + CodeGen/Generic/switch-crit-edge-constant.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31260 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-28 17:04:37 +00:00
Chris Lattner
6fb6ef4d65 Fix a serious bug that caused any x86 vector stuff to infinite loop 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31254 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-28 06:15:26 +00:00
Jim Laskey
def69b92e7 Clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31243 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-27 23:52:51 +00:00
Chris Lattner
8c494ab759 Fix a bug in merged condition handling (CodeGen/Generic/2006-10-27-CondFolding.ll). 
Add many fewer CFG edges and PHI node entries.  If there is a switch which has
the same block as multiple destinations, only add that block once as a successor/phi
node (in the jumptable case)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31242 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-27 23:50:33 +00:00
Jim Laskey
583bd47f77 Switch over from SelectionNodeCSEMap to FoldingSet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31240 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-27 23:46:08 +00:00
Chris Lattner
1c9b2f312d remove debug code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31233 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-27 21:58:03 +00:00
Chris Lattner
d2f9ee9ea7 Codegen cond&cond with two branches. This compiles (f.e.) PowerPC/and-branch.ll to: 
cmpwi cr0, r4, 4
        bgt cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_3: ;entry
        cmplwi cr0, r3, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock

instead of:

        cmpwi cr7, r4, 4
        mfcr r2
        addic r4, r3, -1
        subfe r3, r4, r3
        rlwinm r2, r2, 30, 31, 31
        or r2, r2, r3
        cmplwi cr0, r2, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_1: ;cond_true


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31232 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-27 21:54:23 +00:00
Chris Lattner
571e434a34 Turn conditions like x<Y|z==q into multiple blocks. 
This compiles Regression/CodeGen/X86/or-branch.ll into:

_foo:
        subl $12, %esp
        call L_bar$stub
        movl 20(%esp), %eax
        movl 16(%esp), %ecx
        cmpl $5, %eax
        jl LBB1_1       #cond_true
LBB1_3: #entry
        testl %ecx, %ecx
        jne LBB1_2      #UnifiedReturnBlock
LBB1_1: #cond_true
        call L_bar$stub
        addl $12, %esp
        ret
LBB1_2: #UnifiedReturnBlock
        addl $12, %esp
        ret

instead of:

_foo:
        subl $12, %esp
        call L_bar$stub
        movl 20(%esp), %eax
        movl 16(%esp), %ecx
        cmpl $4, %eax
        setg %al
        testl %ecx, %ecx
        setne %cl
        testb %cl, %al
        jne LBB1_2      #UnifiedReturnBlock
LBB1_1: #cond_true
        call L_bar$stub
        addl $12, %esp
        ret
LBB1_2: #UnifiedReturnBlock
        addl $12, %esp
        ret

And on ppc to:

        cmpwi cr0, r29, 5
        blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
        cmplwi cr0, r30, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock

instead of:

        cmpwi cr7, r4, 4
        mfcr r2
        addic r4, r3, -1
        subfe r30, r4, r3
        rlwinm r29, r2, 30, 31, 31
        and r2, r29, r30
        cmplwi cr0, r2, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31230 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-27 21:36:01 +00:00
Evan Cheng
5270cf1b77 getPreIndexedLoad -> getIndexedLoad. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31209 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-26 21:53:40 +00:00