Commit Graph

81 Commits

Author SHA1 Message Date
Akira Hatanaka
29d525a3ed Add code needed for copying between 64-bit integer and floating pointer
registers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144017 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07 21:35:45 +00:00
Akira Hatanaka
3e3427a5c3 Add support for conditional branch instructions with 64-bit register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141694 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 18:49:17 +00:00
Akira Hatanaka
1acb7df498 Make changes necessary for supporting floating point load and store instructions
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141623 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 01:12:52 +00:00
Akira Hatanaka
43aed32e20 Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141613 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 00:37:28 +00:00
Akira Hatanaka
4391bb75ec Simplify definition of FP move instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141476 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 03:50:18 +00:00
Akira Hatanaka
2ad766851d Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integer
registers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141019 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 20:38:08 +00:00
Jakob Stoklund Olesen
5cd4ee7770 Revert r140731, "Define classes for unary and binary FP instructions and use them to define"
It broke the unit tests.  Please reapply with tests fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140735 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 23:59:28 +00:00
Akira Hatanaka
d42ca4607b Define classes for unary and binary FP instructions and use them to define
multiclasses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140731 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 21:58:01 +00:00
Evan Cheng
3e74d6fdd2 Move TargetRegistry and TargetSelect from Target to Support where they belong.
These are strictly utilities for registering targets and components.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 18:08:43 +00:00
Akira Hatanaka
614051a1c5 Fix handling of double precision loads and stores when Mips1 is targeted.
Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This 
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same 
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137711 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-16 03:51:51 +00:00
Evan Cheng
c60f9b7523 Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 20:59:42 +00:00
Evan Cheng
59ee62d241 - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 03:57:24 +00:00
Akira Hatanaka
794bf17cbe Lower MachineInstr to MC Inst and print to .s files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134661 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 23:56:50 +00:00
Akira Hatanaka
d3ac47f805 Reverse order of operands of address operand mem so that the base operand comes
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.





git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134625 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07 18:57:00 +00:00
Evan Cheng
4db3cffe94 Hide the call to InitMCInstrInfo into tblgen generated ctor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 17:57:27 +00:00
Akira Hatanaka
c4f24eb584 Improve Mips back-end's handling of DBG_VALUE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134224 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 01:04:43 +00:00
Evan Cheng
d5b03f252c Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134030 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 21:14:33 +00:00
Evan Cheng
22fee2dff4 Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 20:07:07 +00:00
Evan Cheng
e837dead3c - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 19:10:37 +00:00
Akira Hatanaka
4552c9a3b3 Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129612 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 21:51:11 +00:00
Akira Hatanaka
0bf3dfbef6 Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129606 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 21:00:26 +00:00
Akira Hatanaka
20ada98de8 Add code for analyzing FP branches. Clean up branch Analysis functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128718 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 17:39:08 +00:00
Akira Hatanaka
1d6b38d9d3 Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128650 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 18:26:17 +00:00
Bruno Cardoso Lopes
81092dc20a Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 17:51:39 +00:00
Jakob Stoklund Olesen
78e6e00922 Remove the isMoveInstr() hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 22:35:46 +00:00
Jakob Stoklund Olesen
600f171486 RISC architectures get their memory operand folding for free.
The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108099 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 19:19:13 +00:00
Jakob Stoklund Olesen
273c14f530 Replace copyRegToReg with copyPhysReg for Mips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108066 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 01:08:31 +00:00
Jakob Stoklund Olesen
3ecf1f0179 Use COPY in targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108063 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10 22:43:03 +00:00
Stuart Hastings
3bf9125933 Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 22:43:56 +00:00
Dan Gohman
34dcc6fadc Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:33:48 +00:00
Evan Cheng
746ad69e08 Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 19:06:44 +00:00
Dan Gohman
9f2cda73e4 No-ops emitted for scheduling don't correspond with anything in the
user's source, so don't arbitrarily assign them a debug location.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103121 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 20:58:01 +00:00
Chris Lattner
c7f3ace20c use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 20:16:16 +00:00
Dale Johannesen
93d6a7e9c2 Teach AnalyzeBranch, RemoveBranch and the branch
folder to be tolerant of debug info following the
branch(es) at the end of a block.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100168 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 01:38:09 +00:00
Bruno Cardoso Lopes
ea98278935 load f64 +0.0 in a cleaner way. This fix part of PR5445
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-19 12:53:04 +00:00
Dan Gohman
864e2efce2 Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90634 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-05 00:44:40 +00:00
Bruno Cardoso Lopes
302525b234 Add proper emission of load/store double to stack slots for mips1 targets!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89821 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-25 00:36:00 +00:00
Bruno Cardoso Lopes
a8173b934f Support fp64 immediate zero, this fixes only part of PR5445
because the testcase is triggering one more bug.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88674 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-13 18:49:59 +00:00
Eli Friedman
23ed52752b Remove unused member functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76960 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-24 07:43:59 +00:00
Torok Edwin
c23197a26f llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-14 16:55:14 +00:00
Torok Edwin
c25e7581b9 assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-11 20:10:48 +00:00
Duncan Sands
430506924d Silence a warning when assertions are turned off.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74779 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-03 16:11:59 +00:00
Evan Cheng
2578ba26e7 Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74580 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-01 01:59:31 +00:00
Dan Gohman
9911405183 Convert Alpha and Mips to use a MachineFunctionInfo subclass to
carry GlobalBaseReg, and GlobalRetAddr too in Alpha's case. This
eliminates the need for them to search through the
MachineRegisterInfo livein list in order to identify these
virtual registers. EmitLiveInCopies is now the only user of the
virtual register portion of MachineRegisterInfo's livein data.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72802 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03 20:30:14 +00:00
Bruno Cardoso Lopes
d3bdf19ce7 Added support for fround, fextend and FP_TO_SINT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72483 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-27 17:23:44 +00:00
Bill Wendling
587daedce2 Change MachineInstrBuilder::addReg() to take a flag instead of a list of
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.

I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-13 21:33:08 +00:00
Chris Lattner
e3a85838da fix some warnings in release-asserts mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67738 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-26 05:28:26 +00:00
Bruno Cardoso Lopes
bdfbb74d34 Removed AFGR32 register class
Handle odd registers allocation in FGR32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67422 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-21 00:05:07 +00:00
Dan Gohman
97357614b5 Factor out the code to add a MachineOperand to a MachineInstrBuilder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64891 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-18 05:45:50 +00:00
Dale Johannesen
948175785d Remove non-DebugLoc versions of BuildMI from IA64, Mips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64438 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-13 02:34:39 +00:00