Commit Graph

199 Commits

Author SHA1 Message Date
Krzysztof Parzyszek
d496e176f0 [Hexagon] Generate instructions for operations on predicate registers
Convert logical operations on general-purpose registers to the correspon-
ding operations on predicate registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242186 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-14 19:30:21 +00:00
Krzysztof Parzyszek
14e60218b6 [Hexagon] Generate "extract" instructions more aggressively
Generate extract instructions (via intrinsics) before the DAG combiner
folds shifts into unrecognizable forms.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242163 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-14 17:07:24 +00:00
Krzysztof Parzyszek
b13f72aa2d [Hexagon] Add support for atomic RMW operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241804 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 14:51:21 +00:00
Krzysztof Parzyszek
a307401165 [Hexagon] Implement commoning of GetElementPtr instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241714 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 19:22:28 +00:00
Krzysztof Parzyszek
e7f45f66a7 [Hexagon] Generate "insert" instructions more aggressively
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241683 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 14:47:34 +00:00
Krzysztof Parzyszek
5d447e9c2a Revert 241681: causes Windows builds to fail
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241682 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 14:34:13 +00:00
Krzysztof Parzyszek
ea2273d00c [Hexagon] Generate "insert" instructions more aggressively
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241681 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 14:22:27 +00:00
Colin LeMahieu
21e6bede12 [Hexagon] Printing packet brackets when asm printing and adding a number of tests that test packet brackets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240051 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-18 20:43:50 +00:00
Colin LeMahieu
6fc90b32e3 [Hexagon] Adding a number of other tests for min/max instructions and loading i1s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239935 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-17 20:29:33 +00:00
Colin LeMahieu
7540f2c60a [Hexagon] Adding some compare tests, fixing existing XFAILed tests, and removing mcpu=hexagonv4 since that's the minimum version anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239917 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-17 17:19:05 +00:00
Colin LeMahieu
360661f1d1 [Hexagon] Adding MC ELF streamer and updating addend relocation test which shows correct ELF symbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239876 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-17 03:06:16 +00:00
Colin LeMahieu
0d6057a14d [Hexagon] Using readobj rather than objdump.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239770 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 21:57:41 +00:00
Colin LeMahieu
c1344684c9 [Hexagon] PC-relative offsets are relative to packet start rather than the offset of the relocation. Set relocation addend and check it's correct in the ELF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239769 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 21:52:13 +00:00
Colin LeMahieu
3a36996b73 [Hexagon] Adding some codegen tests and updating some to match spec.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239690 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 21:46:39 +00:00
Colin LeMahieu
53aa3e0444 [Hexagon] Making intrinsic tests agnostic to register allocation. Narrowing intrinsic parameters to appropriate width.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239634 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-12 19:57:32 +00:00
Colin LeMahieu
c196bfecd6 [Hexagon] Adding decoders for signed operands and ensuring all signed operand types disassemble correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239477 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-10 16:52:32 +00:00
Colin LeMahieu
838271c858 [Hexagon] Adding functionality for searching for compound instruction pairs. Compound instructions reduce slot resource requirements freeing those packet slots up for more instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239307 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-08 16:34:47 +00:00
Colin LeMahieu
750b351b76 [Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239161 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-05 16:00:11 +00:00
Colin LeMahieu
3a665e02da Shouldn't be XFAIL'ed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239103 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 21:49:43 +00:00
Colin LeMahieu
4e8f68f245 Revert r239095 incorrect test tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239102 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 21:32:42 +00:00
Colin LeMahieu
60b4c7fc30 [Hexagon] Adding functionality for duplexing. Duplexing is a way to compress commonly used pairs of instructions in order to reduce code size. The test case duplex.ll normally would be 8 bytes, assign register to 0 and jump to link register. After duplexing this is only 4 bytes. This also tests the HexagonMCShuffler code path which is used to make sure duplexed instructions still follow slot requirements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239095 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-04 21:16:16 +00:00
Colin LeMahieu
0a999e4d3a [Hexagon] Test doesn't work on all platforms. At any rate the uninitialized variable issue was fixed. Removing re-registering ASM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238949 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-03 18:00:45 +00:00
Colin LeMahieu
4009e89061 [Hexagon] Reapply 238772 OSABI was not correctly set, added empty_elf test to make sure it is.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238947 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-03 17:34:16 +00:00
Rafael Espindola
9be6a55ba0 Revert "[Hexagon] Adding basic ELF relocation generation and testing advanced relaxation codepath."
This reverts commit r238748.

It broke the msan bot:

http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/4372/steps/check-llvm%20msan/logs/stdio

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238772 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-01 19:20:47 +00:00
Colin LeMahieu
8a6a249f6b [Hexagon] Adding basic ELF relocation generation and testing advanced relaxation codepath.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238748 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-01 14:51:26 +00:00
Colin LeMahieu
0ace3c01f7 [Hexagon] Disassembling, printing, and emitting instructions a whole-bundle at a time which is the semantic unit for Hexagon. Fixing tests to use the new format. Disabling tests in the direct object emission path for a followup patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238556 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-29 14:44:13 +00:00
Brendon Cahoon
abf95a22c4 [Hexagon] Generate hardware loop for a vectorized loop
The induction variable in the vectorized loop wasn't
recognized properly, so a hardware loop wasn't generated.

Differential Revision: http://reviews.llvm.org/D9722


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237388 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-14 20:36:19 +00:00
Brendon Cahoon
6912fe6f35 [Hexagon] Remove dead constant assignment in hardware loop pass
After converting a loop to a hardware loop, the pass should remove
any unnecessary instructions from the old compare-and-branch
code. This patch removes a dead constant assignment that was
used in the compare instruction.

Differential Revision: http://reviews.llvm.org/D9720


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237373 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-14 17:31:40 +00:00
Brendon Cahoon
23b0065f29 [Hexagon] Check for underflow/wrap in hardware loop pass
If the loop trip count may underflow or wrap, the compiler should
not generate a hardware loop since the trip count will be
incorrect.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237365 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-14 14:15:08 +00:00
Brendon Cahoon
a036cd4093 [Hexagon] Generate loop1 instruction for nested loops
loop1 is for the outer loop and loop0 is for the inner loop.

Differential Revision: http://reviews.llvm.org/D9680


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237266 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-13 17:56:03 +00:00
Brendon Cahoon
e55e117ad3 [Hexagon] Generate hardware loop when loop has a critical edge
The hardware loop pass should try to generate a hardware loop
instruction when the original loop has a critical edge.

Differential Revision: http://reviews.llvm.org/D9678


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237258 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-13 14:54:24 +00:00
Sundeep Kushwaha
891914aef8 [PATCH] [HEXAGON] Add a test program to verify calling convention
for large struct return by value.

Differential Revision: http://reviews.llvm.org/D9709



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237170 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-12 20:13:10 +00:00
Brendon Cahoon
74b576041a [Hexagon] Generate more hardware loops
Refactored parts of the hardware loop pass to generate
more. Also, added more tests.

Differential Revision: http://reviews.llvm.org/D9568


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236896 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-08 20:18:21 +00:00
Brendon Cahoon
7fd56b1e4a [Hexagon] Update AnalyzeBranch, etc target hooks
Improved the AnalyzeBranch, InsertBranch, and RemoveBranch
functions in order to handle more of our branch instructions.
This requires changes to analyzeCompare and PredicateInstructions.
Specifically, we've added support for new value compare jumps,
improved handling of endloop, added more compare instructions,
and improved support for predicate instructions.

Differential Revision: http://reviews.llvm.org/D9559


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236876 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-08 16:16:29 +00:00
Duncan P. N. Exon Smith
e56023a059 IR: Give 'DI' prefix to debug info metadata
Finish off PR23080 by renaming the debug info IR constructs from `MD*`
to `DI*`.  The last of the `DIDescriptor` classes were deleted in
r235356, and the last of the related typedefs removed in r235413, so
this has all baked for about a week.

Note: If you have out-of-tree code (like a frontend), I recommend that
you get everything compiling and tests passing with the *previous*
commit before updating to this one.  It'll be easier to keep track of
what code is using the `DIDescriptor` hierarchy and what you've already
updated, and I think you're extremely unlikely to insert bugs.  YMMV of
course.

Back to *this* commit: I did this using the rename-md-di-nodes.sh
upgrade script I've attached to PR23080 (both code and testcases) and
filtered through clang-format-diff.py.  I edited the tests for
test/Assembler/invalid-generic-debug-node-*.ll by hand since the columns
were off-by-three.  It should work on your out-of-tree testcases (and
code, if you've followed the advice in the previous paragraph).

Some of the tests are in badly named files now (e.g.,
test/Assembler/invalid-mdcompositetype-missing-tag.ll should be
'dicompositetype'); I'll come back and move the files in a follow-up
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236120 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-29 16:38:44 +00:00
Brendon Cahoon
2afd045e03 [Hexagon] Use constant extenders to fix up hardware loops
Use a loop instruction with a constant extender for a hardware
loop instruction that is too far away from the start of the loop.
This is cheaper than changing the SA register value.

Differential Revision: http://reviews.llvm.org/D9262


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235882 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-27 14:16:43 +00:00
Sundeep Kushwaha
9cb570cb75 [PATCH] [Hexagon] Adding a test case for calling convention.
http://reviews.llvm.org/D9241



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235754 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-24 19:22:02 +00:00
Krzysztof Parzyszek
de0d4bf1d4 [Hexagon] Shrink-wrap stack frame (Hexagon-specific)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235603 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 16:05:39 +00:00
Krzysztof Parzyszek
69c69df308 [Hexagon] Add testcases for stack alignment and variable-sized objects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235602 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 15:12:49 +00:00
Krzysztof Parzyszek
bbe056c9bc [Hexagon] Some cleanup of instruction selection code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235552 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-22 21:17:00 +00:00
Krzysztof Parzyszek
3c55df1e84 [Hexagon] Use A2_tfrsi for constant pool and jump table addresses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235535 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-22 18:25:53 +00:00
Krzysztof Parzyszek
a42f6b9a58 [Hexagon] Patterns for frame index with offset for isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235418 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-21 21:28:03 +00:00
David Blaikie
32b845d223 [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction
See r230786 and r230794 for similar changes to gep and load
respectively.

Call is a bit different because it often doesn't have a single explicit
type - usually the type is deduced from the arguments, and just the
return type is explicit. In those cases there's no need to change the
IR.

When that's not the case, the IR usually contains the pointer type of
the first operand - but since typed pointers are going away, that
representation is insufficient so I'm just stripping the "pointerness"
of the explicit type away.

This does make the IR a bit weird - it /sort of/ reads like the type of
the first operand: "call void () %x(" but %x is actually of type "void
()*" and will eventually be just of type "ptr". But this seems not too
bad and I don't think it would benefit from repeating the type
("void (), void () * %x(" and then eventually "void (), ptr %x(") as has
been done with gep and load.

This also has a side benefit: since the explicit type is no longer a
pointer, there's no ambiguity between an explicit type and a function
that returns a function pointer. Previously this case needed an explicit
type (eg: a function returning a void() function was written as
"call void () () * @x(" rather than "call void () * @x(" because of the
ambiguity between a function returning a pointer to a void() function
and a function returning void).

No ambiguity means even function pointer return types can just be
written alone, without writing the whole function's type.

This leaves /only/ the varargs case where the explicit type is required.

Given the special type syntax in call instructions, the regex-fu used
for migration was a bit more involved in its own unique way (as every
one of these is) so here it is. Use it in conjunction with the apply.sh
script and associated find/xargs commands I've provided in rr230786 to
migrate your out of tree tests. Do let me know if any of this doesn't
cover your cases & we can iterate on a more general script/regexes to
help others with out of tree tests.

About 9 test cases couldn't be automatically migrated - half of those
were functions returning function pointers, where I just had to manually
delete the function argument types now that we didn't need an explicit
function type there. The other half were typedefs of function types used
in calls - just had to manually drop the * from those.

import fileinput
import sys
import re

pat = re.compile(r'((?:=|:|^|\s)call\s(?:[^@]*?))(\s*$|\s*(?:(?:\[\[[a-zA-Z0-9_]+\]\]|[@%](?:(")?[\\\?@a-zA-Z0-9_.]*?(?(3)"|)|{{.*}}))(?:\(|$)|undef|inttoptr|bitcast|null|asm).*$)')
addrspace_end = re.compile(r"addrspace\(\d+\)\s*\*$")
func_end = re.compile("(?:void.*|\)\s*)\*$")

def conv(match, line):
  if not match or re.search(addrspace_end, match.group(1)) or not re.search(func_end, match.group(1)):
    return line
  return line[:match.start()] + match.group(1)[:match.group(1).rfind('*')].rstrip() + match.group(2) + line[match.end():]

for line in sys.stdin:
  sys.stdout.write(conv(re.search(pat, line), line))

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235145 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-16 23:24:18 +00:00
Jan Vesely
a017ce21ba Revert revisions r234755, r234759, r234760
Revert "Remove default in fully-covered switch (to fix Clang -Werror -Wcovered-switch-default)"
Revert "R600: Add carry and borrow instructions. Use them to implement UADDO/USUBO"
Revert "LegalizeDAG: Try to use Overflow operations when expanding ADD/SUB"

Using overflow operations fails CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll
on hexagon, nvptx, and r600. Revert while I investigate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234768 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-13 17:47:15 +00:00
Krzysztof Parzyszek
fcc330abfe Allow memory intrinsics to be tail calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234764 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-13 17:16:45 +00:00
Jan Vesely
187ac42686 LegalizeDAG: Try to use Overflow operations when expanding ADD/SUB
v2: consider BooleanContents when processing overflow

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewers: resistor, jholewinsky (nvidia parts)
Differential Revision: http://reviews.llvm.org/D6340

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234755 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-13 15:32:01 +00:00
Krzysztof Parzyszek
4654bc762e Expand MUX instructions early on Hexagon
This time with all files included.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233696 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 13:35:12 +00:00
Krzysztof Parzyszek
b7c19b3cc9 Revert 233694. Weak SVN-fu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233695 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 13:32:32 +00:00
Krzysztof Parzyszek
af4ad2d843 Expand MUX instructions early on Hexagon
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233694 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-31 13:29:17 +00:00
Krzysztof Parzyszek
07121ea974 [Hexagon] Add support for vector instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232728 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-19 16:33:08 +00:00