Michael Liao
d9d09600ee
Enable lowering ZERO_EXTEND/ANY_EXTEND to PMOVZX from SSE4.1
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166486 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23 17:34:00 +00:00
Michael Liao
44c2d61b67
Add support for FP_ROUND from v2f64 to v2f32
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- Due to the current matching vector elements constraints in
ISD::FP_ROUND, rounding from v2f64 to v4f32 (after legalization from
v2f32) is scalarized. Add a customized v2f32 widening to convert it
into a target-specific X86ISD::VFPROUND to work around this
constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165631 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 16:53:28 +00:00
Michael Liao
b8150d8523
Enhance PR11334 fix to support extload from v2f32/v4f32
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- Fix an remaining issue of PR11674 as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163528 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 18:33:51 +00:00
Craig Topper
fd49821c35
Convert FMA4 patterns to use target specific nodes instead of intrinsics to align with FMA3.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162829 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 07:18:25 +00:00
Nadav Rotem
d60cb11afd
When unsafe math is used, we can use commutative FMAX and FMIN. In some cases
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this allows for better code generation.
Added a new DAGCombine transformation to convert FMAX and FMIN to FMANC and
FMINC, which are commutative.
For example:
movaps %xmm0, %xmm1
movsd LC(%rip), %xmm0
minsd %xmm1, %xmm0
becomes:
minsd LC(%rip), %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162187 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-19 13:06:16 +00:00
Michael Liao
7091b2451d
fix PR11334
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- FP_EXTEND only support extending from vectors with matching elements.
This results in the scalarization of extending to v2f64 from v2f32,
which will be legalized to v4f32 not matching with v2f64.
- add X86-specific VFPEXT supproting extending from v4f32 to v2f64.
- add BUILD_VECTOR lowering helper to recover back the original
extending from v4f32 to v2f64.
- test case is enhanced to include different vector width.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161894 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14 21:24:47 +00:00
Craig Topper
4feb647283
Implement proper handling for pcmpistri/pcmpestri intrinsics. Requires custom handling in DAGISelToDAG due to limitations in TableGen's implicit def handling. Fixes PR11305.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161318 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-06 06:22:36 +00:00
Elena Demikhovsky
1503aba4a0
Added FMA functionality to X86 target.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161110 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01 12:06:00 +00:00
Bill Wendling
56cb229866
Remove tabs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160477 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-19 00:11:40 +00:00
Craig Topper
2a5dc43bd9
Use XOP vpcom intrinsics in patterns instead of a target specific SDNode type. Remove the custom lowering code that selected the SDNode type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158279 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-09 17:02:24 +00:00
Elena Demikhovsky
1da5867236
ZERO_EXTEND/SIGN_EXTEND/TRUNCATE optimization for AVX2
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155309 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-22 09:39:03 +00:00
Craig Topper
9204074598
Change type profile for vpermv back to using operand type for the mask argument to match intrinsic behavior. Add a bitcast to the lowering code to convert mask from v8i32 to v8f32 for vpermps.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154798 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 06:43:40 +00:00
Craig Topper
8325c11d47
Merge vpermps/vpermd and vpermpd/vpermq SD nodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154782 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 00:41:45 +00:00
Craig Topper
ca9ee66e36
Fix SDTypeProfile for vpermps. The mask operand should be v8i32.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154781 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 00:12:20 +00:00
Elena Demikhovsky
73c504af9d
Added VPERM optimization for AVX2 shuffles
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154761 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-15 11:18:59 +00:00
Nadav Rotem
e611378a6e
Reapply 154396 after fixing a test.
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Original message:
Modify the code that lowers shuffles to blends from using blendvXX to vblendXX.
blendV uses a register for the selection while Vblend uses an immediate.
On sandybridge they still have the same latency and execute on the same execution ports.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154483 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 06:40:27 +00:00
Eric Christopher
a139051654
Temporarily revert this patch to see if it brings the buildbots back.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154425 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10 19:33:16 +00:00
Nadav Rotem
50e64cfe6e
Modify the code that lowers shuffles to blends from using blendvXX to vblendXX.
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blendv uses a register for the selection while vblend uses an immediate.
On sandybridge they still have the same latency and execute on the same execution ports.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154396 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10 14:33:13 +00:00
Chad Rosier
abd6674166
Fix a regression from r147481.
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Original commit message from r147481:
DAGCombine for transforming 128->256 casts into a vmovaps, rather
then a vxorps + vinsertf128 pair if the original vector came from a load.
Fix:
Unaligned loads need to generate a vmovups.
rdar://10974078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152366 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-09 02:00:48 +00:00
Jia Liu
44de83a7f6
some comment fix for X86 and ARM
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-19 02:03:36 +00:00
Jia Liu
31d157ae1a
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-18 12:03:15 +00:00
Craig Topper
6e94e68b75
Remove the last of the old vector_shuffle patterns from X86 isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150795 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17 07:02:34 +00:00
Craig Topper
233a64846e
Move old movl vector_shuffle patterns. Not needed anymore since vector_shuffles shouldn't reach isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150462 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-14 08:14:53 +00:00
Craig Topper
7505626acd
Still more vector_shuffle pattern removal.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150365 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13 07:23:41 +00:00
Craig Topper
3b17bf9a7c
Recommit r150328. Previous test failures should be fixed by r150360.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150362 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13 05:10:10 +00:00
NAKAMURA Takumi
7f42e9886e
Revert r150328, "Remove more vector_shuffle patterns."
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It caused 3 failures on pre-penryn and non-x86(generic) hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150357 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-13 00:10:15 +00:00
Craig Topper
cc9231a05d
Remove more vector_shuffle patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150328 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-12 08:14:35 +00:00
Craig Topper
26f927951b
Remove more vector_shuffle patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150321 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-12 01:07:34 +00:00
Craig Topper
a819c397e7
Remove some patterns for matching vector_shuffle instructions since vector_shuffles should be custom lowered before isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150299 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11 07:43:35 +00:00
Craig Topper
5b209e84f4
Add target specific node for PMULUDQ. Change patterns to use it and custom lower intrinsics to it. Use it instead of intrinsic to handle 64-bit vector multiplies.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149807 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 03:14:49 +00:00
Elena Demikhovsky
dcabc7bca9
Optimization for SIGN_EXTEND operation on AVX.
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Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32
extensions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149600 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 09:10:43 +00:00
Craig Topper
86c7c583a3
Move some XOP patterns into instruction definition. Replae VPCMOV intrinsic patterns with custom lowering to a target specific nodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149216 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-30 01:10:15 +00:00
Craig Topper
969ba287cd
Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148933 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-25 06:43:11 +00:00
Craig Topper
dfc8e470b6
Add comments near load pattern fragments indicating that all integer vector loads are promoted to v2i64 or v4i64 so that no one tries to reintroduce pattern fragments for other types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148771 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 03:03:17 +00:00
Craig Topper
2b21fbaf11
Remove pattern fragments for v32i8, v16i16, v8i32, v16i8, v8i16, and v4i32 loads. All integer vector loads are promoted to v2i64 or v4i64 so these pattern fragments can never match. Fix or remove patterns that used these fragments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148672 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 00:06:44 +00:00
Craig Topper
1906d32e55
Combine X86 CMPPD and CMPPS node types. Simplifies selection code and pattern matching.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148670 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-22 23:36:02 +00:00
Craig Topper
67609fd0eb
Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86 ISD node types into only two node types. Simplifying opcode selection and pattern matching.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148667 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-22 22:42:16 +00:00
Craig Topper
ed2e13d667
Add target specific ISD node types for SSE/AVX vector shuffle instructions and change all the code that used to create intrinsic nodes to create the new nodes instead.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-22 19:15:14 +00:00
Craig Topper
1a7700a3fa
Merge 128-bit and 256-bit SHUFPS/SHUFPD handling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148466 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-19 08:19:12 +00:00
Craig Topper
b3982da7d2
Merge X86 SHUFPS and SHUFPD node types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147394 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-31 23:50:21 +00:00
Craig Topper
ab44d3cf49
Remove an unused X86ISD node type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146833 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-17 19:16:44 +00:00
Craig Topper
d93e4c3496
Remove some remants of the old palign pattern fragment that were still hanging around. Also remove a cast from inside getShuffleVPERM2X128Immediate and getShuffleVPERMILPImmediate since the only caller already had done the cast.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-11 19:12:35 +00:00
Craig Topper
34671b812a
Merge floating point and integer UNPCK X86ISD node types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145926 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 08:21:25 +00:00
Craig Topper
ec24e61ab0
Merge VPERM2F128/VPERM2I128 ISD node types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 07:47:51 +00:00
Craig Topper
316cd2a2c5
Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node type for VPERMILPD/PS. Add instruction selection support for VINSERTI128/VEXTRACTI128.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145483 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 06:25:25 +00:00
Craig Topper
70b883b3a7
Add X86 instruction selection for VPERM2I128 when AVX2 is enabled. Merge VPERMILPS/VPERMILPD detection since they are pretty similar.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145238 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-28 10:14:51 +00:00
Craig Topper
38034c568c
Merge 128-bit and 256-bit X86ISD node types for VPERMILPS and VPERMILPD. Simplify some shuffle lowering code since V1 can never be UNDEF due to canonalizing that occurs when shuffle nodes are created.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145153 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-26 22:55:48 +00:00
Craig Topper
06cb680779
Collapse X86ISD node types for PUNPCKH*, PUNPCKL*, UNPCKLP*, and UNPCKHP* to not be type specific. Now we just have integer high and low and floating point high and low. Pattern matching will choose the correct instruction based on the vector type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145148 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-26 20:47:44 +00:00
Craig Topper
705f2431a0
Remove 256-bit specific node types for UNPCKHPS/D and instead use the 128-bit versions and let the operand type disinquish. Also fix the load form of the v8i32 patterns for these to realize that the load would be promoted to v4i64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145126 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-24 22:57:10 +00:00
Craig Topper
f475a55bd4
Remove AVX2 specific X86ISD node types for PUNPCKH/L and instead just reuse the 128-bit versions and let the vector type distinguish.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-24 22:20:08 +00:00