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Author SHA1 Message Date
Jim Grosbach
b5aa11f2d6 fix silly typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110831 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 17:32:46 +00:00
Jim Grosbach
7166e622d7 Add a target triple, as the runtime library invocation varies a bit by 
platform. It's apparently "bl __muldf3" on linux, for example. Since that's
not what we're checking here, it's more robust to just force a triple. We
just wwant to check that the inline FP instructions are only generated
on cpus that have them."



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110830 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 17:31:12 +00:00
Evan Cheng
e1f0859789 Fix test and re-enable it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110829 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 17:25:51 +00:00
Jakob Stoklund Olesen
dfa28b157d Fix a FIXME. The SlotIndex::Slot enum should be private. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110826 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 16:50:17 +00:00
Dan Gohman
3cc5d13f58 Temporarily disable some failing tests, until they can be 
properly investigated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110825 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 16:36:07 +00:00
Jim Grosbach
fcba5e6b64 cortex m4 has floating point support, but only single precision. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110810 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 15:44:15 +00:00
Dan Gohman
f63fed141e Temporarily disable some failing tests, until they can be 
properly investigated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110808 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 15:09:00 +00:00
Bill Wendling
de2b151dbf Consider this code snippet: 
float t1(int argc) {
  return (argc == 1123) ? 1.234f : 2.38213f;
}

We would generate truly awful code on ARM (those with a weak stomach should look
away):

_t1:
  movw   r1, #1123
  movs   r2, #1
  movs   r3, #0
  cmp    r0, r1
  mov.w  r0, #0
  it     eq
  moveq  r0, r2
  movs   r1, #4
  cmp    r0, #0
  it     ne
  movne  r3, r1
  adr    r0, #LCPI1_0
  ldr    r0, [r0, r3]
  bx     lr

The problem was that legalization was creating a cascade of SELECT_CC nodes, for
for the comparison of "argc == 1123" which was fed into a SELECT node for the ?:
statement which was itself converted to a SELECT_CC node. This is because the
ARM back-end doesn't have custom lowering for SELECT nodes, so it used the
default "Expand".

I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this
testcase, but can obviously be expanded to include more cases.

Now we generate this, which looks optimal to me:

_t1:
  movw   r1, #1123
  movs   r2, #0
  cmp    r0, r1
  adr    r0, #LCPI0_0
  it     eq
  moveq  r2, #4
  ldr    r0, [r0, r2]
  bx     lr
  .align  2
LCPI0_0:
  .long   1075344593  @ float 2.382130e+00
  .long   1067316150  @ float 1.234000e+00



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110799 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 08:43:16 +00:00
Evan Cheng
7b4d31176e Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110798 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 07:17:46 +00:00
Evan Cheng
8d62e713ea ArchV7M implies HW division instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110797 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 07:00:16 +00:00
Evan Cheng
cb5ce6e62b ArchV6T2, V7A, and V7M implies Thumb2; Archv7A implies NEON. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110796 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:57:53 +00:00
Evan Cheng
d6b4632256 Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110795 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:51:54 +00:00
Daniel Dunbar
345a9a6269 MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110794 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:37:20 +00:00
Daniel Dunbar
5747b13af8 MC/ARM: Split mnemonic on '.' characters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110793 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:37:16 +00:00
Daniel Dunbar
fa315de8f4 MC/ARM: Fill in ARMOperand::dump a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110792 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:37:12 +00:00
Daniel Dunbar
3c14ca47fc llvm-mc: Add -show-inst-operands, for dumping the parsed instruction representation before matching. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110791 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:37:09 +00:00
Daniel Dunbar
b3cb696794 MCAsmParser: Add dump() hook to MCParsedAsmOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110790 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:37:04 +00:00
Daniel Dunbar
4d39b6728d tblgen/AsmMatcher: Treat '.' in assembly strings as a token separator. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110789 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:36:59 +00:00
Daniel Dunbar
8462b30548 MC/ARM: Add an ARMOperand class for condition codes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110788 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:36:53 +00:00
Evan Cheng
ee34987fd5 Really control isel of barrier instructions with cpu feature. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110787 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:36:31 +00:00
Evan Cheng
c7569ed4e4 Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit 
instructions: dmb, dsb, isb, msr, and mrs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110786 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:30:38 +00:00
Evan Cheng
11db068721 - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the 
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
  instructions).
- Added tests for memory barrier codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:22:01 +00:00
Daniel Dunbar
3483acabf0 MC/ARM: Switch to using the generated match functions instead of stub implementations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110783 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 05:24:50 +00:00
Daniel Dunbar
a7ac688d55 MC/ARM: Enable generation of the ARM asm matcher, not that it can do much. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110782 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 05:09:20 +00:00
Daniel Dunbar
3bcd9f7902 ARM: Mark some disassembler only instructions as not available for matching -- 
for some reason they have a very odd MCInst form where the operands overlap, but
I haven't dug in to find out why yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110781 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 04:46:13 +00:00
Daniel Dunbar
9db683b06c ARM: Quote $p in an asm string. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110780 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 04:46:10 +00:00
Daniel Dunbar
a9ba5fe2bd tblgen/AsmMatcher: Downgrade instructions with tied operands to a debug-only warning, for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110779 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 04:46:08 +00:00
Owen Anderson
2d0f2470ff Improve indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110778 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 04:24:25 +00:00
Bruno Cardoso Lopes
1a76359347 Remove AVX 256-bit cast intrinsics now that clang is using __builtin_shufflevector for those 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110772 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 02:15:33 +00:00
Bruno Cardoso Lopes
9fb2ffd568 Remove AVX 256-bit unpack and interleave intrinsics now that clang is using __builtin_shufflevector for those 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110769 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 01:44:11 +00:00
Bruno Cardoso Lopes
b89c631b77 Remove AVX 256-bit shuffle intrinsics now that clang is using __builtin_shufflevector for those 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110767 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 01:18:26 +00:00
Bill Wendling
d771041828 Update test to match output of optimize compares for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110765 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 01:05:02 +00:00
Oscar Fuentes
e1fadb1dc6 CMake: corrections on LLVM.cmake external services. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110763 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 00:51:32 +00:00
Bill Wendling
38ae997e63 Handle ARM compares as well as converting for ARM adds, subs, and thumb2's adds. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110762 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 00:23:00 +00:00
Bill Wendling
0cce3dd326 Mark ARM compare instructions as isCompare. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110761 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 00:22:27 +00:00
Rafael Espindola
2d643ef328 Make it possible to set the cpu used for codegen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110759 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 00:15:13 +00:00
Dan Gohman
4ee87398e8 When analyzing loop exit conditions combined with and and or, don't 
make any assumptions about when the two conditions will agree on when
to permit the loop to exit. This fixes PR7845.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110758 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 00:12:36 +00:00
Daniel Dunbar
f4452c37d0 lto: Fix an inverted conditional which prevented the addition of symbols scraped 
from inline assembly, except in cases where they had already been seen (in which
case they would get added twice).
 - I can't see how this ever worked...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110757 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 00:11:19 +00:00
Daniel Dunbar
8d0843dcff lto: Fix gratuitous memory leaks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110756 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 00:11:17 +00:00
Bob Wilson
9a1c189d9e Add a separate ARM instruction format for Saturate instructions. 
(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!!  Two of them were already out of sync.  I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.)  Add support for encoding these instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110754 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 00:01:18 +00:00
Oscar Fuentes
0a16b22e64 Avoid multiple definition warnings when both config.h and 
llvm-config.h are included.

This is the cmake counterpart of r110547. See bug #7809.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110753 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 23:48:22 +00:00
Daniel Dunbar
e41d90094c lto: Reduce nesting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110752 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 23:46:46 +00:00
Daniel Dunbar
b06913dd18 LTOModule.cpp: Fix numerous style issues. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110751 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 23:46:39 +00:00
Dan Gohman
af08a36bd6 Rename and reorder the arguments to isImpliedCond, for consistency and clarity. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110750 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 23:46:30 +00:00
Eric Christopher
ae321ed287 We already have this as OperandNode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110748 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 23:46:20 +00:00
Evan Cheng
3611d9e25d CBZ and CBNZ are implemented. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110745 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 23:27:11 +00:00
Bruno Cardoso Lopes
045573ce21 Add AVX matching patterns to Packed Bit Test intrinsics. 
Apply the same approach of SSE4.1 ptest intrinsics but
create a new x86 node "testp" since AVX introduces
vtest{ps}{pd} instructions which set ZF and CF depending
on sign bit AND and ANDN of packed floating-point sources.

This is slightly different from what the "ptest" does.
Tests comming with the other 256 intrinsics tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110744 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 23:25:42 +00:00
Owen Anderson
625051be7e Now that we're using ConstantRange to represent potential values, make use of that represenation to 
create constraints from comparisons other than eq/neq.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110742 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 23:20:01 +00:00
Bill Wendling
bb47d3b471 The optimize comparisons pass removes the "cmp" instruction this is checking for. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110739 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 22:16:05 +00:00
Nate Begeman
e32ea923de Add test for recent instcombine vector shuffle enhancement 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110737 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 21:58:00 +00:00