Commit Graph

5415 Commits

Author SHA1 Message Date
Eric Christopher
bb54d21495 Add some debugging output into fast isel as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152844 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15 21:33:44 +00:00
Eric Christopher
8f2a88d734 Add another debug statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152843 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15 21:33:41 +00:00
Nadav Rotem
6431ff96be When optimizing certain BUILD_VECTOR nodes into other BUILD_VECTOR nodes, add the new node into the work list because there is a potential for further optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152784 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15 08:49:06 +00:00
Bill Wendling
5a89434236 Add a xform to the DAG combiner.
Transform:

        (fsub x, (fadd x, y)) -> (fneg y) and
        (fsub x, (fadd y, x)) -> (fneg y)

if 'unsafe math' is specified.
<rdar://problem/7540295>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152777 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15 05:12:00 +00:00
Bill Wendling
7bf116acd4 Insert the debugging instructions in one fell-swoop so that it doesn't call the
expensive "getFirstTerminator" call. This reduces the time of compilation in
PR12258 from >10 minutes to < 10 seconds.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152704 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-14 07:14:25 +00:00
Evan Cheng
a03d366c88 Fortify r152675 a bit. Although I'm not able to come up with a test case that would trigger the truncation case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152678 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13 22:16:11 +00:00
Evan Cheng
84387ea5f5 DAG combine incorrectly optimize (i32 vextract (v4i16 load $addr), c) to
(i16 load $addr+c*sizeof(i16)) and replace uses of (i32 vextract) with the
i16 load. It should issue an extload instead: (i32 extload $addr+c*sizeof(i16)).

rdar://11035895


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152675 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13 22:00:52 +00:00
Bill Wendling
7d6fc212c2 Add a return type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152614 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13 05:52:28 +00:00
Bill Wendling
bf565702dc Inline the d'tor and add an anchor instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152613 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13 05:51:56 +00:00
Bill Wendling
091306099d Refactor the SelectionDAG's 'dump' methods into their own .cpp file.
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152611 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13 05:47:27 +00:00
Stepan Dyatkovskiy
3d3abe0852 llvm::SwitchInst
Renamed methods caseBegin, caseEnd and caseDefault with case_begin, case_end, and case_default.
Added some notes relative to case iterators.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152532 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-11 06:09:17 +00:00
Benjamin Kramer
d5f7690651 Give dagcombiner's worklist some inline capacity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152454 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10 00:23:58 +00:00
Craig Topper
fac2598149 Use uint16_t to store instruction implicit uses and defs. Reduces static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152301 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08 08:22:45 +00:00
Stepan Dyatkovskiy
c10fa6c801 Taken into account Duncan's comments for r149481 dated by 2nd Feb 2012:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20120130/136146.html

Implemented CaseIterator and it solves almost all described issues: we don't need to mix operand/case/successor indexing anymore. Base iterator class is implemented as a template since it may be initialized either from "const SwitchInst*" or from "SwitchInst*".

ConstCaseIt is just a read-only iterator.
CaseIt is read-write iterator; it allows to change case successor and case value.

Usage of iterator allows totally remove resolveXXXX methods. All indexing convertions done automatically inside the iterator's getters.

Main way of iterator usage looks like this:
SwitchInst *SI = ... // intialize it somehow

for (SwitchInst::CaseIt i = SI->caseBegin(), e = SI->caseEnd(); i != e; ++i) {
  BasicBlock *BB = i.getCaseSuccessor();
  ConstantInt *V = i.getCaseValue();
  // Do something.
}

If you want to convert case number to TerminatorInst successor index, just use getSuccessorIndex iterator's method.
If you want initialize iterator from TerminatorInst successor index, use CaseIt::fromSuccessorIndex(...) method.

There are also related changes in llvm-clients: klee and clang.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152297 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08 07:06:20 +00:00
Andrew Trick
953be893e8 misched preparation: rename core scheduler methods for consistency.
We had half the API with one convention, half with another. Now was a
good time to clean it up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152255 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 23:00:49 +00:00
Andrew Trick
47c144505b misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.
ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation.

ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class.

ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target.

Specific changes:
- Removed driver code from ScheduleDAG. clearDAG is the only interface needed.

- Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls.

- Added ScheduleDAGInstrs::begin()/end() public API.

- Moved Sequence into the driver layer, which is specific to the scheduling algorithm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152208 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 05:21:52 +00:00
Andrew Trick
84b454d1a2 misched preparation: modularize schedule emission.
ScheduleDAG has nothing to do with how the instructions are scheduled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152206 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 05:21:44 +00:00
Andrew Trick
73ba69b684 misched preparation: modularize schedule printing.
ScheduleDAG will not refer to the scheduled instruction sequence.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152205 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 05:21:40 +00:00
Andrew Trick
4c72720427 misched preparation: modularize schedule verification.
ScheduleDAG will not refer to the scheduled instruction sequence.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152204 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 05:21:36 +00:00
Andrew Trick
dbdca36af8 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152203 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 05:21:32 +00:00
Andrew Trick
56b94c52c9 Cleanup in preparation for misched: Move DAG visualization logic.
Soon, ScheduleDAG will not refer to the BB.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152177 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:18:22 +00:00
Andrew Trick
acddd4963d whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152175 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:18:15 +00:00
Andrew Trick
084e179f09 Cleanup: DAG building is specific to either SD or MI scheduling. Not part of the target interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152174 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07 00:18:12 +00:00
Evan Cheng
03be3622aa Extend r148086 to check for [r +/- reg] address mode. This fixes queens performance regression (due to increased register pressure from overly aggressive pre-inc formation).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152162 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 23:33:32 +00:00
Owen Anderson
afd3d56b9d Make it possible for a target to mark FSUB as Expand. This requires providing a default expansion (FADD+FNEG), and teaching DAGCombine not to form FSUBs post-legalize if they are not legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152079 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 00:29:31 +00:00
Bill Wendling
c27faccb3c Fix warnings about adding a bool to a string.
Patch by Sean Silva!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152042 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05 19:29:36 +00:00
Craig Topper
e4fd907e72 Use uint16_t to store register overlaps to reduce static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04 10:43:23 +00:00
James Molloy
391016025a Fix a codegen fault in which log2 or exp2 could be dead-code eliminated even though they could have sideeffects.
Only allow log2/exp2 to be converted to an intrinsic if they are declared "readnone".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151807 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01 14:32:18 +00:00
Benjamin Kramer
f1820b54e4 LegalizeIntegerTypes: Reorder operations in the "big shift by small amount" optimization, making the lives of later passes easier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151722 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29 13:27:00 +00:00
Evan Cheng
4bfcd4acbc Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151645 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 18:51:51 +00:00
Benjamin Kramer
a3b2121ccf Fix off-by one in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151644 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 18:37:06 +00:00
Benjamin Kramer
3bf15ced2b LegalizeIntegerTypes: Reenable the large shift with small amount optimization.
To avoid problems with zero shifts when getting the bits that move between words
we use a trick: first shift the by amount-1, then do another shift by one. When
amount is 0 (and size 32) we first shift by 31, then by one, instead of by 32.

Also fix a latent bug that emitted the low and high words in the wrong order
when shifting right.

Fixes PR12113.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151637 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 17:58:00 +00:00
Daniel Dunbar
20bd5296ce Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 15:36:07 +00:00
Nadav Rotem
1c239200e4 Code cleanup following CR by Duncan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151627 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 14:13:19 +00:00
Nadav Rotem
21ef70ed4f Fix a bug in the code that builds SDNodes from vector GEPs.
When the GEP index is a vector of pointers, the code that calculated the size
of the element started from the vector type, and not the contained pointer type.
As a result, instead of looking at the data element pointed by the vector, this
code used the size of the vector. This works for 32bit members (on 32bit
systems), but not for other types. Added code to peel the vector type and
added a test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151626 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 11:54:05 +00:00
Evan Cheng
ec52aaa12f Some ARM implementaions, e.g. A-series, does return stack prediction. That is,
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.

Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.

rdar://8979299


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 06:42:03 +00:00
Hal Finkel
f77c03a859 Don't crash when a glue node contains an internal CopyToReg
This is necessary to support the existing ppc lowering code for indirect calls.
Fixes PR12071.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151373 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24 17:53:59 +00:00
Benjamin Kramer
8b93ff298c SDAGBuilder: Remove register sets that were never read and prune dead code surrounding it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151364 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24 14:01:17 +00:00
Pete Cooper
d18134f116 Turn avx insert intrinsic calls into INSERT_SUBVECTOR DAG nodes and remove duplicate patterns for selecting the intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151342 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24 03:51:49 +00:00
Eric Christopher
178606d92e If the Address of a variable is an argument then treat the entire
variable declaration as an argument because we want that address
anyhow for our debug information.

This seems to fix rdar://9965111, at least we have more debug
information than before and from reading the assembly it appears
to be the correct location.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151335 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24 01:59:08 +00:00
Eric Christopher
5b13ed1ac9 Tabs, formatting and long lines oh my!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151334 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24 01:59:01 +00:00
Bill Wendling
9e8ceb0bac Allow an integer to be converted into an MMX type when it's used in an inline
asm.
<rdar://problem/10106006>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151303 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 23:25:25 +00:00
Eric Christopher
0822e010d1 More newline cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151235 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 03:39:43 +00:00
Eric Christopher
244136770b Add some handy-dandy newlines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151234 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 03:39:39 +00:00
Michael J. Spencer
c9c137b463 Properly emit _fltused with FastISel. Refactor to share code with SDAG.
Patch by Joe Groff!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151183 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22 19:06:13 +00:00
Craig Topper
44d23825d6 Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22 05:59:10 +00:00
James Molloy
6259dcdc57 Teach the DAGCombiner that certain loadext nodes followed by ANDs can be converted to zeroexts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150957 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-20 12:02:38 +00:00
Eric Christopher
9b5d6b860c Ignore the lifetime intrinsics in fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150848 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17 23:03:39 +00:00
James Molloy
6afa3f744a Remove extraneous #include and spelling mistake introduced in r150669.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150670 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16 09:48:07 +00:00
James Molloy
6660c05da3 Modify the algorithm when traversing the DAGCombiner's worklist to be O(log N) for all operations. This fixes a horrible worst case with lots of nodes where 99% of the time was being spent in std::remove.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150669 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-16 09:17:04 +00:00