Commit Graph

2871 Commits

Author SHA1 Message Date
Vladimir Medic
c0fad4d9fd Fix bug in .gpword directive parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194570 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 13:18:04 +00:00
Zoran Jovanovic
1206f1968b Support for microMIPS trap instruction with immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 13:15:03 +00:00
Vladimir Medic
c7ebe50276 This patch fixes a bug in floating point operands parsing, when instruction alias uses default register operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194562 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 09:48:53 +00:00
Tim Northover
59e648e3c8 ARM: diagnose invalid system LDM/STM
The system LDM and STM instructions can't usually writeback to the base
register. The one exception is when an LDM is actually an exception-return
(i.e. contains PC in the register list).

(There's already a test that "ldm sp!, {r0-r3, pc}^" works, which is why there
is no positive test).

rdar://problem/15223374

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194512 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 21:32:41 +00:00
Chad Rosier
13c83a2a09 [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar
copy in MC layer. Added the MC layer tests.  Fixed triple setting in test cases.

Patch by Ana Pazos <apazos@codeaurora.org>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194501 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 19:13:08 +00:00
Artyom Skrobov
ef572e31e2 [ARM] Add support for MVFR2 which is new in ARMv8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194416 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 19:56:13 +00:00
Chad Rosier
30b2a19f3b [AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194394 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 18:04:07 +00:00
Jim Grosbach
dc7eb3e023 X86: Assembly files with .cfi_cfa_def shouldn't hit llvm_unreachable()
On darwin, when trying to create compact unwind info, a .cfi_cfa_def
directive would case an llvm_unreachable() to be hit. Back off when we
see this directive and generate the regular DWARF style eh_frame.

rdar://15406518

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194285 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 22:33:06 +00:00
Artyom Skrobov
2b01682aa7 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (Thumb encodings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194263 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 16:25:50 +00:00
Artyom Skrobov
c5c991bf31 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194262 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 16:17:14 +00:00
Artyom Skrobov
fa840ba402 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194261 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 16:16:30 +00:00
Zoran Jovanovic
c9af1add85 Test for microMIPS trap instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194258 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 14:55:31 +00:00
Matheus Almeida
de712386cd [mips][msa] Update encoding of LDI instruction.
The encoding was updated in MSA r1.07.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194255 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 10:43:11 +00:00
Artyom Skrobov
1b91231347 [ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194253 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 09:16:31 +00:00
Zoran Jovanovic
9f471750fa Support for microMIPS trap instructions 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194205 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-07 14:35:24 +00:00
Vladimir Medic
2263a2ca72 Implement gpword directive for mips, test case added. Stype changes using clang-format are also included.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194145 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 11:27:05 +00:00
Jiangning Liu
8458f371b8 Implement AArch64 Neon instruction set Perm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 03:35:27 +00:00
Jiangning Liu
258115258f Implement AArch64 Neon instruction set Bitwise Extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194118 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 02:25:49 +00:00
Tim Northover
f635ab8eab ARM: permit bare dmb/dsb/isb aliases on Cortex-M0
Cortex-M0 supports these 32-bit instructions despite being Thumb1 only
(mostly). We knew about that but not that the aliases without the default "sy"
operand were also permitted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194094 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 21:36:02 +00:00
Jiangning Liu
3ff3a8aa75 Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194085 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 17:42:05 +00:00
Hao Liu
591c2f738a Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post).
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194043 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 03:39:32 +00:00
Zoran Jovanovic
5c042162be Support for microMIPS branch instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193992 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 14:53:22 +00:00
Chad Rosier
1a035dd6df [AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193816 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 22:36:59 +00:00
Chad Rosier
f7ba489730 [AArch64] Add diagnostic tests for NEON scalar shift immediate instructions (see: r193790).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193798 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 20:11:32 +00:00
Chad Rosier
1d28917dc3 [AArch64] Add support for NEON scalar shift immediate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193790 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 19:28:44 +00:00
Amara Emerson
c2884320fe [AArch64] Make the use of FP instructions optional, but enabled by default.
This adds a new subtarget feature called FPARMv8 (implied by NEON), and
predicates the support of the FP instructions and registers on this feature.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193739 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 09:32:11 +00:00
Tom Roeder
4ca9a2a0ad This commit adds some (but not all) of the x86-64 relocations that are not
currently supported in the ELF object writer, along with a simple test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193709 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 18:47:25 +00:00
Artyom Skrobov
3f04b50686 [ARM] NEON instructions were erroneously decoded from certain invalid encodings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193705 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 18:10:09 +00:00
Chad Rosier
f853a034a1 [AArch64] Add support for NEON scalar floating-point compare instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193691 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 15:19:37 +00:00
Zoran Jovanovic
1aaf43c2a2 Support for microMIPS jump instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193623 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 16:38:59 +00:00
Bernard Ogden
c777b2e58c Test cleanup for v8 instructions
Add some missing tests, factor out a test not specific to v8 into
its own file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193611 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 14:16:09 +00:00
Bernard Ogden
47c6d17b1c ARM: Add subtarget feature for CRC
Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend.

Differential Revision: http://llvm-reviews.chandlerc.com/D2036

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193599 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 09:47:35 +00:00
Joerg Sonnenberger
72580780a9 Move the STT_FILE symbols out of the normal symbol table processing for
ELF. They can overlap with the other symbols, e.g. if a source file
"foo.c" contains a function "foo" with a static variable "c".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 01:06:17 +00:00
Rafael Espindola
136660484d Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193548 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 22:17:19 +00:00
Rafael Espindola
61e4743913 Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193547 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 22:11:47 +00:00
Rafael Espindola
82c2703167 Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193546 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 22:05:05 +00:00
Rafael Espindola
1df3e17fde Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193539 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 21:12:15 +00:00
Rafael Espindola
9540074467 Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193538 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 21:06:12 +00:00
Rafael Espindola
ade09c7fe7 Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193537 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 20:59:41 +00:00
Rafael Espindola
e2f60cf7f1 Convert another llc -filetype=obj test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193536 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 20:54:33 +00:00
Lang Hames
3d478aee8e Return early from getUnconditionalBranchTargetOpValue if the branch target is
an MCExpr, in order to avoid writing an encoded zero value in the immediate
field.

When getUnconditionalBranchTargetOpValue is called with an MCExpr target, we
don't know what the final immediate field value should be. We shouldn't
explicitly set the immediate field to an encoded zero value as zero is encoded
with a non-zero bit pattern. This leads to bits being set that pollute the
final immediate value. The nature of the encoding is such that the polluted
bits only affect very large immediate values, explaining why this hasn't
caused problems earlier.

Fixes <rdar://problem/15155975>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193535 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 20:51:11 +00:00
Rafael Espindola
164bd156fc Convert a llc -filetype=obj test into a llvm-mc test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193534 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 20:40:20 +00:00
Logan Chien
23125d02d9 [arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.

To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.

Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.

This commit changes the test cases:

* Several .eabi_attribute directives in
  2010-09-29-mc-asm-header-test.ll are removed because the .fpu
  directive already cover the functionality.

* In the Cortex-A15 test case, the value for
  Tag_Advanced_SIMD_arch has be changed from 1 to 2,
  which is more precise.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28 17:51:12 +00:00
Tim Northover
c8f4e5db29 ARM: allow .thumb_func to be separated from symbol definition
When assembling, a .thumb_func directive is supposed to be applicable to the
next symbol definition, even if there are intervening directives. We were
racing ahead to try and find it, and this commit should fix the issue.

Patch by Gabor Ballabas

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193403 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-25 12:49:50 +00:00
Tim Northover
abe3aa3520 ARM: tweak test to pass on all platforms
A TableGen indeterminacy means that the reason for the failure can
vary, and Windows gets the other option.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193394 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-25 07:34:56 +00:00
Tim Northover
44edc227c7 ARM: Mark double-precision instructions as such
This prevents us from silently accepting invalid instructions on (for example)
Cortex-M4 with just single-precision VFP support.

No tests for the extra Pat Requires because they're essentially assertions: the
affected code should have been lowered to libcalls before ISel.

rdar://problem/15302004

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193354 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-24 15:49:39 +00:00
Tim Northover
e2dee623e0 ARM: add a couple more NEON predicates.
The fused multiply instructions were added in VFPv4 but are still NEON
instructions, in particular they shouldn't be available on a Cortex-M4 not
matter how floaty it is.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193342 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-24 12:48:05 +00:00
Tim Northover
eac623a18b ARM: mark various aliases with their architecture requirements.
If an alias inherits directly from InstAlias then it doesn't get any default
"Requires" values, so llvm-mc will allow it even on architectures that don't
support the underlying instruction.

This tidies up the obvious VFP and NEON cases I found.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193340 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-24 12:22:58 +00:00
Zoran Jovanovic
ef713e27b1 Added tests for microMIPS relocations 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193332 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-24 10:55:00 +00:00
Tim Northover
cdd776d13f ARM: fix assert on unpredictable POP instruction.
POP instructions are aliased to the ARM LDM variants but have different syntax.
This caused two problems: we tried to access a non-existent operand to annotate
the '!', and the error message didn't make much sense.

With some vigorous hand-waving in the error message both problems can be
fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193322 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-24 09:37:18 +00:00