Commit Graph

207 Commits

Author SHA1 Message Date
Torok Edwin
c25e7581b9 assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-11 20:10:48 +00:00
Evan Cheng
261ce1d5f8 Remove TargetInstrInfo::CommuteChangesDestination and added findCommutedOpIndices which returns the operand indices which are swapped (when applicable). This allows for some code clean up and future enhancements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75264 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10 19:15:51 +00:00
Evan Cheng
d923fc621f Move getInstrOperandRegClass from the scheduler to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70950 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-05 00:30:09 +00:00
Evan Cheng
c781a243a3 In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all.
VirtRegMap keeps track of allocations so it knows what's not used. As a horrible hack, the stack coloring can color spill slots with *free* registers. That is, it replace reload and spills with copies from and to the free register. It unfold instructions that load and store the spill slot and replace them with register using variants.

Not yet enabled. This is part 1. More coming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70787 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-03 18:32:42 +00:00
Dan Gohman
88c7af096b Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize
it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 21:06:25 +00:00
Dan Gohman
f8c7394781 Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.
This will be used to replace things like X86's MOV32to32_.

Enhance ScheduleDAGSDNodesEmit to be more flexible and robust
in the presense of subregister superclasses and subclasses. It
can now cope with the definition of a virtual register being in
a subclass of a use.

Re-introduce the code for recording register superreg classes and
subreg classes. This is needed because when subreg extracts and
inserts get coalesced away, the virtual registers are left in
the correct subclass.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68961 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 15:38:05 +00:00
Dan Gohman
73099b1058 Add comments to INSERT_SUBREG, EXTRACT_SURBEG, SUBREG_TO_REG,
and IMPLICIT_DEF.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68949 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 15:12:29 +00:00
Dale Johannesen
c1c9d7e6a9 Describe tail merging's use of InsertBranch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65062 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-19 19:40:21 +00:00
Evan Cheng
dc54d317e7 Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty
suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64124 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-09 07:14:22 +00:00
Evan Cheng
770bcc7b15 Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-06 17:43:24 +00:00
Evan Cheng
4350eb86a7 Add TargetInstrInfo::isSafeToMoveRegisterClassDefs. It returns true if it's safe to move an instruction which defines a value in the register class. Replace pre-splitting specific IgnoreRegisterClassBarriers with this new hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63936 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-06 17:17:30 +00:00
Evan Cheng
04ee5a1d92 Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-20 19:12:24 +00:00
Dan Gohman
2b00aebda9 Fix a typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61035 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-15 17:26:50 +00:00
Dan Gohman
c54baa2d43 Split foldMemoryOperand into public non-virtual and protected virtual
parts, and add target-independent code to add/preserve
MachineMemOperands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60488 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-03 18:43:12 +00:00
Dan Gohman
cbad42cfd1 Add more const qualifiers. This fixes build breakage from r59540.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59542 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-18 19:49:32 +00:00
Evan Cheng
23066288fd For now, don't split live intervals around x87 stack register barriers. FpGET_ST0_80 must be right after a call instruction (and ADJCALLSTACKUP) so we need to find a way to prevent reload of x87 registers between them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58230 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-27 07:14:50 +00:00
Evan Cheng
95a3f0d99e Add storeRegTo{StackSlot|Addr} and loadRegFrom{StackSlot|Addr} descriptions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58164 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-25 23:08:22 +00:00
Dan Gohman
8c8b2a89f9 Fix a typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57832 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-20 15:58:02 +00:00
Dan Gohman
8e8b8a223c Const-ify several TargetInstrInfo methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57622 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-16 01:49:15 +00:00
Evan Cheng
a6548d0f29 Clarify meaning of copyRegToReg's return value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57449 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-13 17:30:56 +00:00
Cedric Venet
c93457053c - small bug corrected: incorrect iterator type.
- fix to please VS: add a return after an assert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55380 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-26 19:49:04 +00:00
Owen Anderson
940f83e772 Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
was inserted or not.  This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55375 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-26 18:03:31 +00:00
Owen Anderson
44eb65cf58 Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54802 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-14 22:49:33 +00:00
Dan Gohman
61e804f22b Clarify the comments here, to make slightly more clear the
difference in purpose of TargetInstrInfo and TargetInstrDesc,
which isn't immediately obvious from the name.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53683 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-16 16:02:59 +00:00
Owen Anderson
f660c171c8 Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction
Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53058 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-02 23:41:07 +00:00
Dan Gohman
4406604047 Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.

Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.

This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52943 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-01 00:05:16 +00:00
Evan Cheng
58dcb0e0cd Add option to commuteInstruction() which forces it to create a new (commuted) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52308 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16 07:33:11 +00:00
Bill Wendling
9f8fea3531 Constify the machine instruction passed into the
"is{Trivially,Really}ReMaterializable" methods.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51001 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-12 20:54:26 +00:00
Nicolas Geoffray
52e724ad7e Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49809 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-16 20:10:13 +00:00
Evan Cheng
ca1267c02b Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48995 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-31 20:40:39 +00:00
Christopher Lamb
c929823525 Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48412 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-16 03:12:01 +00:00
Evan Cheng
da47e6e0d0 Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-15 00:03:38 +00:00
Christopher Lamb
6634e26aa1 Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects.
Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48329 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-13 05:47:01 +00:00
Evan Cheng
f20db15954 Added CommuteChangesDestination(). This returns true if commuting the specified
machine instr will change its definition register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47166 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-15 18:21:33 +00:00
Evan Cheng
5fd79d0560 It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46893 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-08 21:20:40 +00:00
Evan Cheng
a844bdeab3 SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-02 04:07:54 +00:00
Chris Lattner
a22edc82ca Simplify the side effect stuff a bit more and make licm/sinking
both work right according to the new flags.

This removes the TII::isReallySideEffectFree predicate, and adds
TII::isInvariantLoad. 

It removes NeverHasSideEffects+MayHaveSideEffects and adds
UnmodeledSideEffects as machine instr flags.  Now the clients
can decide everything they need.

I think isRematerializable can be implemented in terms of the
flags we have now, though I will let others tackle that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45843 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-10 23:08:24 +00:00
Chris Lattner
d3f99e2bbf split TargetInstrDesc out into its own header file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45696 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07 07:33:08 +00:00
Chris Lattner
749c6f6b5e rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07 07:27:27 +00:00
Chris Lattner
682b8aed07 remove a dead method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45694 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07 06:47:10 +00:00
Chris Lattner
0ff23966fe Rename all the M_* flags to be namespace qualified enums, and switch
all clients over to using predicates instead of these flags directly.
These are now private values which are only to be used to statically
initialize the tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45692 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07 06:42:05 +00:00
Chris Lattner
e32d765f99 add more and significantly better comments to the rest of the machineinstr
flags that can be set.  Add predicates for the ones lacking it, and switch
some clients over to using the predicates instead of Flags directly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45690 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07 06:21:53 +00:00
Chris Lattner
13cea0bcef add some mroe comments, add a isImplicitDef() method, add
isConditionalBranch() and isUnconditionalBranch() methods.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45688 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07 05:38:38 +00:00
Chris Lattner
8f707e15fb rename hasVariableOperands() -> isVariadic(). Add some comments.
Evan, please review the comments I added to getNumDefs to make sure
that they are accurate, thx.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45687 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07 05:19:29 +00:00
Chris Lattner
4764189298 Move M_* flags down in the file. Move SchedClass up in the
TargetInstrDescriptor class and shrink to 16-bits, saving a 
word in TargetInstrDescriptor.  Add some comments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45686 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07 05:06:49 +00:00
Chris Lattner
349c495200 Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45680 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07 03:13:06 +00:00
Chris Lattner
cc8cd0cbf1 remove MachineOpCode typedef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45679 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07 02:48:55 +00:00
Chris Lattner
ba6da5d5b7 remove some uses of MachineOpCode, move getSchedClass
into TargetInstrDescriptor from TargetInstrInfo.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45678 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07 02:46:03 +00:00
Chris Lattner
8ca5c67c6e Add predicates methods to TargetOperandInfo, and switch all clients
over to using them, instead of diddling Flags directly.  Change the
various flags from const variables to enums.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45677 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07 02:39:19 +00:00
Chris Lattner
69244300b8 Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
that it is cheap and efficient to get.

Move a variety of predicates from TargetInstrInfo into 
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around.  Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.

Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45674 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07 01:56:04 +00:00