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1040 Commits

Author SHA1 Message Date
Craig Topper
5fefc00bac Make F16C feature flag imply AVX rather than just checking both at the patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190775 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-16 04:29:58 +00:00
Ben Langmuir
a247e9d42b Add the remaining Intel SHA instructions 
Also assembly/disassembly tests, and for sha256rnds2, aliases with an explicit
xmm0 dependency.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190754 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-14 15:03:21 +00:00
Preston Gurd
94dc6540a8 Adds support for Atom Silvermont (SLM) - -march=slm 
Implements Instruction scheduler latencies for Silvermont,
using latencies from the Intel Silvermont Optimization Guide.

Auto detects SLM.

Turns on post RA scheduler when generating code for SLM.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190717 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-13 19:23:28 +00:00
Ben Langmuir
1f1bd9a54d Partial support for Intel SHA Extensions (sha1rnds4) 
Add basic assembly/disassembly support for the first Intel SHA
instruction 'sha1rnds4'. Also includes feature flag, and test cases.

Support for the remaining instructions will follow in a separate patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190611 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-12 15:51:31 +00:00
Elena Demikhovsky
f9d2d2dc89 AVX-512: implemented extractelement with variable index. 
Added parsing of mask register and "zeroing" semantic, like {%k1} {z}.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190595 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-12 08:55:00 +00:00
Craig Topper
704e8d41fe Add neverHasSideEffects=1 on a couple move instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190259 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-08 00:50:45 +00:00
Elena Demikhovsky
2fb982aa72 AVX-512: added SQRT, VRSQRT14, VCOMISS, VUCOMISS, VRCP14, VPABS 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189472 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-28 11:21:58 +00:00
Elena Demikhovsky
d371d4f0f4 AVX-512: added conversion instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189349 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-27 13:54:04 +00:00
Elena Demikhovsky
92bfb54770 AVX-512: Added shuffle instructions - 
VPSHUFD, VPERMILPS, VMOVDDUP, VMOVLHPS, VMOVHLPS, VSHUFPS, VALIGN
 single and double forms.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189215 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-26 12:45:35 +00:00
Elena Demikhovsky
38cd21a3e9 AVX-512: Added more patterns for VMOVSS, VMOVSD, VMOVD, VMOVQ 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188786 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-20 11:00:29 +00:00
Craig Topper
b5e1d5b46f Move AVX and non-AVX replication inside a couple multiclasses to avoid repeating each instruction for both individually. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188743 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-20 04:24:14 +00:00
Elena Demikhovsky
3491d67d3a AVX-512: Added VMOVD, VMOVQ, VMOVSS, VMOVSD instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188637 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-18 13:08:57 +00:00
Benjamin Kramer
75311b7b4d X86: Turn fp selects into mask operations. 
double test(double a, double b, double c, double d) { return a<b ? c : d; }

before:
_test:
	ucomisd	%xmm0, %xmm1
	ja	LBB0_2
	movaps	%xmm3, %xmm2
LBB0_2:
	movaps	%xmm2, %xmm0

after:
_test:
	cmpltsd	%xmm1, %xmm0
	andpd	%xmm0, %xmm2
	andnpd	%xmm3, %xmm0
	orpd	%xmm2, %xmm0

Small speedup on Benchmarks/SmallPT

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187706 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-04 12:05:16 +00:00
Elena Demikhovsky
f3e3417e65 AVX-512 set: added VEXTRACTPS instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187705 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-04 10:46:07 +00:00
Elena Demikhovsky
8395251c0a Added INSERT and EXTRACT intructions from AVX-512 ISA. 
All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms.
Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors.
Added lowering for EXTRACT/INSERT subvector for 512-bit vectors.
Added a test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187491 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-31 11:35:14 +00:00
Craig Topper
418eb3df74 Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax. 
Patch by Richard Mitton.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187476 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-31 02:47:52 +00:00
Craig Topper
9564c1e9b8 Remove some errant space charcters in mnemonic strings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186932 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-23 06:45:34 +00:00
Craig Topper
1011c13f15 More Intel syntax alias fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186814 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-22 09:58:07 +00:00
Craig Topper
5e08ce288a Change %xmm0 to XMM0 in Intel side of asm strings for PBLENDVB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186812 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-22 09:22:49 +00:00
Elena Demikhovsky
40e071c1eb Removed PackedDouble domain from scalar instructions. Added more formats for the scalar stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183626 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-09 07:37:10 +00:00
Michael Liao
9a508ef64a [PATCH] Fix VGATHER* operand constraints 
Add earlyclobber constaints to prevent input register being allocated as
the output register because, according to Intel spec [1], "If any pair
of the index, mask, or destination registers are the same, this
instruction results a UD fault."

---
[1] http://software.intel.com/sites/default/files/319433-014.pdf



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183327 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 18:12:26 +00:00
Elena Demikhovsky
f8cd1ee516 Removed SSEPacked domain from all forms (AVX, SSE, signed, unsigned) scalar compare instructions, like COMISS, COMISD. 
No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182371 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-21 12:04:22 +00:00
Preston Gurd
acccd2edc8 Corrected Atom latencies for SSE SQRT instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181346 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-07 19:57:34 +00:00
Rafael Espindola
dc0981d3e0 Put VMOVPQIto64rr in the VRPDI class. 
Patch by Joshua Magee.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180842 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-01 13:00:16 +00:00
Benjamin Kramer
753981784f X86: Now that we have a canonical form for vector integer abs, match it into pabs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180600 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-26 12:05:21 +00:00
Jakob Stoklund Olesen
b4f60e9f77 Annotate the remaining x86 instructions with SchedRW lists. 
Now all x86 instructions that have itinerary classes also have SchedRW
lists. This is required before the new scheduling models can be used.

There are still unannotated instructions remaining, but they don't have
itinerary classes either.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178051 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-26 18:24:22 +00:00
Jakob Stoklund Olesen
68d832a04d Remove IIC_DEFAULT from X86Schedule.td 
All the instructions tagged with IIC_DEFAULT had nothing in common, and
we already have a NoItineraries class to represent untagged
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177937 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-25 23:12:41 +00:00
Jakob Stoklund Olesen
3c987aead2 Model prefetches and barriers as loads. 
It's not yet clear if these instructions need a more careful model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177599 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-20 23:09:53 +00:00
Jakob Stoklund Olesen
eab5f7678b Add a catch-all WriteSystem SchedWrite type. 
This is used for all the expensive system instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177598 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-20 23:09:50 +00:00
Jakob Stoklund Olesen
dcb4d349b6 Annotate the remaining SSE MOV instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177592 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-20 22:37:16 +00:00
Jakob Stoklund Olesen
2e9aadda63 Annotate SSE horizontal and integer instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177591 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-20 22:37:13 +00:00
Jakob Stoklund Olesen
279ad470b6 Add some missing SSE annotations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177540 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-20 16:56:39 +00:00
Jakob Stoklund Olesen
361706a718 Annotate various null idioms with SchedRW lists. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177461 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-19 23:23:31 +00:00
Jakob Stoklund Olesen
f2914c3b2b Annotate SSE float conversions with SchedRW lists. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177460 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-19 23:23:29 +00:00
Jakob Stoklund Olesen
9beae49622 Add SchedRW annotations to most of X86InstrSSE.td. 
We hitch a ride with the existing OpndItins class that was used to add
instruction itinerary classes in the many multiclasses in this file.

Use the link provided by the X86FoldableSchedWrite.Folded to find the
right SchedWrite for folded loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177326 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-18 22:01:35 +00:00
Nadav Rotem
dd7a300c10 Unaligned loads should use the VMOVUPS opcode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177130 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-14 23:49:44 +00:00
Craig Topper
4aee1bb222 Fix inconsistent usage of PALIGN and PALIGNR when referring to the same instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173667 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-28 06:48:25 +00:00
Craig Topper
c2cbcc3acf Combine AVX and SSE forms of MOVSS and MOVSD into the same multiclasses so they get instantiated together. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172704 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-17 06:59:42 +00:00
Craig Topper
29344a6349 Simplify nested strconcats in X86 td files since strconcat can take more than 2 arguments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172379 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-14 07:46:34 +00:00
Craig Topper
33160cf376 Create a single multiclass for SSE and AVX version of MOVL/MOVH. Prevents needing to specify everything twice. No functional change intended 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172378 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-14 07:26:58 +00:00
Benjamin Kramer
08219ea2b4 X86: Add patterns for X86ISD::VSEXT in registers. 
Those can occur when something between the sextload and the store is on the same
chain and blocks isel. Fixes PR14887.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172353 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-13 11:37:04 +00:00
Craig Topper
df3bf55d49 Remove unnecessary # tokens at the beginning and end of defm names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171694 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-07 05:04:39 +00:00
Craig Topper
f564a9389d Fix suffix handling for parsing and printing of cvtsi2ss, cvtsi2sd, cvtss2si, cvttss2si, cvtsd2si, and cvttsd2si to match gas behavior. 
cvtsi2* should parse with an 'l' or 'q' suffix or no suffix at all. No suffix should be treated the same as 'l' suffix. Printing should always print a suffix. Previously we didn't parse or print an 'l' suffix.
cvtt*2si/cvt*2si should parse with an 'l' or 'q' suffix or not suffix at all. No suffix should use the destination register size to choose encoding. Printing should not print a suffix.

Original 'l' suffix issue with cvtsi2* pointed out by Michael Kuperstein.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171668 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-06 20:39:29 +00:00
Craig Topper
3af9323228 Merge SSE and AVX instruction definitions for scalar forms of SQRT, RSQRT, and RCP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171356 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-02 08:00:39 +00:00
Craig Topper
3cca7df7c7 Merge SSE and AVX instruction definitions for PSHUFD/PSHUFHW/PSHUFLW. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171355 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-02 07:27:49 +00:00
Rafael Espindola
9478673ce0 Revert 171351. It broke MC/X86/x86-32-avx.s. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171352 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-02 01:35:11 +00:00
Craig Topper
b511048cd0 Merge SSE and AVX instruction definitions for scalar forms of SQRT, RSQRT, and RCP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171351 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-01 20:53:20 +00:00
Craig Topper
117e4d2e19 Remove unused argument from a multiclass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171340 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-01 03:42:44 +00:00
Craig Topper
76f94fd361 Merge intrinsic instruction definitions for SSE and AVX versions of RCPPS and RSQRTPS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171339 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-01 03:30:21 +00:00
Craig Topper
42ab0d75ab Remove 2 unused multiclasses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171338 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-01 02:02:45 +00:00