Commit Graph

66559 Commits

Author SHA1 Message Date
Rafael Espindola
cc3acee7b3 Add support for .value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117922 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 15:29:07 +00:00
Rafael Espindola
484291c273 Implement .weakref.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117911 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 14:28:48 +00:00
Bill Wendling
69661191ce Move instruction encoding bits into the parent class and remove the temporary
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117906 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 06:00:39 +00:00
Bill Wendling
504fb4fb8e More tests to XFAIL. The arm-and-txt-peephole.ll test passes even when the
peephole optimizer is disabled. That's not good at all.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117905 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 05:59:43 +00:00
Bill Wendling
9e7cb3d243 The testcase is now XFAILed. Sorry about the breakage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 05:50:55 +00:00
Bill Wendling
59707e8055 Disable because peephole is disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 05:48:44 +00:00
Chris Lattner
acc473fcf9 "mov[zs]x (mem), GR16" are not ambiguous: the mem
must be 8 bits.  Support this memory form.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117902 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 05:41:10 +00:00
Chris Lattner
b501d4f673 Implement enough of the missing instalias support to get
aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 05:34:34 +00:00
Owen Anderson
b8d14a6611 Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117900 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 05:23:58 +00:00
Chris Lattner
22bc5c4184 rename InstructionInfo -> MatchableInfo since it now
represents InstAliases as well.  Rename 
isAssemblerInstruction -> Validate since that is what
it does (modulo the ARM $lane hack).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117899 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 05:06:45 +00:00
Chris Lattner
c2d67bbf80 refactor initialization of InstructionInfo to be sharable between
instructions and InstAliases.  Start creating InstructionInfo's
for Aliases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117898 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 04:53:48 +00:00
Chris Lattner
4164f6bbbf make the asm matcher emitter reject instructions that have comments
in their asmstring.  Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 04:44:29 +00:00
Chris Lattner
5bc9387806 refactor InstructionInfo to not have a pointer to CodeGenInstruction
member, and make isAssemblerInstruction() a method (pushing some code
around inside it).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117895 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 04:34:44 +00:00
Chris Lattner
c76e80ded7 define a new CodeGenInstAlias. It has an asmstring and operand list for now,
todo: the result field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117894 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 04:05:41 +00:00
Chris Lattner
c240bb0ede factor the operand list (and related fields/operations) out of
CodeGenInstruction into its own helper class.  No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117893 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 04:03:32 +00:00
Chris Lattner
79b3cddfa2 avoid needless throw/catch/rethrow, stringref'ize some simple stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117892 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 03:19:09 +00:00
Chris Lattner
f780811456 eliminate the old InstFormatName which is always "AsmString",
simplify CodeGenInstruction. No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117891 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 02:15:23 +00:00
Chris Lattner
4a74ee7203 all predicates on an MnemonicAlias must be AssemblerPredicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117890 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 02:09:21 +00:00
Chris Lattner
1de8823578 change the singleton register handling code to be based on Record*'s
instead of strings, simplifying it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117889 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 01:47:07 +00:00
Chris Lattner
02bcbc97fb Give AsmMatcherInfo a CodeGenTarget, which simplifies a bunch of
argument passing.  Consolidate all SingletonRegister detection
and handling into a new 
InstructionInfo::getSingletonRegisterForToken method instead of
having it scattered about.  No change in generated .inc files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117888 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 01:37:30 +00:00
Chris Lattner
4d43d0fd99 move FlattenVariants out of AsmMatcherEmitter into a shared
CodeGenInstruction::FlattenAsmStringVariants method.  Use it
to simplify the code in AsmWriterInst, which now no longer 
needs to worry about variants.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117886 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 01:07:14 +00:00
Chris Lattner
52de0ef922 add a FIXME, $lane in ARM is an issue that needs to be resolved before
this can start rejecting instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117885 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 00:51:32 +00:00
Chris Lattner
4d1189f385 reject instructions that contain a \n in their asmstring. Mark
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117884 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 00:46:16 +00:00
Chandler Carruth
25592eb52c Add a specialization for 'long', a hole in the set of fundamental
specializations provided here. This is a little annoying because its size
changes from platform to platform. If possible, I may follow up with a patch
that uses standard constants to simplify much of this, but assuming for now
that was avoided for a reason.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117880 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 22:57:03 +00:00
Eric Christopher
b698a56dd4 Revert r117876 for now, it's causing more testsuite failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 22:42:55 +00:00
Bill Wendling
b3747706fc Disable the peephole optimizer until 186.crafty on armv6 is fixed. This is what
looks like is happening:

Without the peephole optimizer:
  (1)   sub     r6, r6, #32
        orr     r12, r12, lr, lsl r9
        orr     r2, r2, r3, lsl r10
  (x)   cmp     r6, #0
        ldr     r9, LCPI2_10
        ldr     r10, LCPI2_11
  (2)   sub     r8, r8, #32
  (a)   movge   r12, lr, lsr r6
  (y)   cmp     r8, #0
LPC2_10:
        ldr     lr, [pc, r10]
  (b)   movge   r2, r3, lsr r8

With the peephole optimizer:
        ldr     r9, LCPI2_10
        ldr     r10, LCPI2_11
  (1*)  subs    r6, r6, #32
  (2*)  subs    r8, r8, #32
  (a*)  movge   r12, lr, lsr r6
  (b*)  movge   r2, r3, lsr r8

(1) is used by (x) for the conditional move at (a). (2) is used by (y) for the
conditional move at (b). After the peephole optimizer, these the flags resulting
from (1*) are ignored and only the flags from (2*) are considered for both
conditional moves.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 22:07:12 +00:00
Nicolas Geoffray
7a5a3f75eb Attach a GCModuleInfo to a MachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117867 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 20:38:38 +00:00
Chris Lattner
d6d9dd9f5e fix a crash on:
let Constraints = "$val = $dst", Defs = [EFLAGS] in, isCodeGenOnly = 1 {

we now get:

X86InstrCompiler.td:653:52: error: Expected class, def, defm, multiclass or let definition
let Constraints = "$val = $dst", Defs = [EFLAGS] in, isCodeGenOnly = 1 {
                                                   ^



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117863 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 19:27:15 +00:00
Chris Lattner
150d20e8fc fix the !eq operator in tblgen to return a bit instead of an int.
Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117862 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 19:22:57 +00:00
Chris Lattner
a4a3a5e3c2 two changes: make the asmmatcher generator ignore ARM pseudos properly,
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117861 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 19:15:18 +00:00
Chris Lattner
39ee036f40 reapply r117858 with apparent editor malfunction fixed (somehow I
got a dulicated line).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117860 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 19:10:56 +00:00
Chris Lattner
8b2f0822f3 revert r117858 while I check out a failure I missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 19:05:32 +00:00
Chris Lattner
efa53760fe the asm matcher can't handle operands with modifiers (like ${foo:bar}).
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the 
instruction 'isCodeGenOnly'.

Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are 
doing this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117858 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 18:48:12 +00:00
Chris Lattner
a33b93f7f1 sketch out the planned instruction alias mechanism, add some comments about
how the push/pop mnemonic aliases are wrong.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117857 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 18:43:46 +00:00
Duncan Sands
4590766580 Factorize the duplicated logic for choosing the right argument
calling convention out of the fast and normal ISel files, and
into the calling convention TD file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117856 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 13:21:44 +00:00
Duncan Sands
e26032d5b2 Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86,
which has the same logic specified in the CallingConv TD file.
This brings FastISel in line with the standard X86 ISel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117855 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 13:02:38 +00:00
Duncan Sands
0acfa8db3f Explain the return value of CCAssignFn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 10:29:14 +00:00
Rafael Espindola
7be2c33193 Add support for files with more than 65280 sections. No testcase since
it would be a bit too big :-)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117849 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-31 00:16:26 +00:00
Eric Christopher
76d61478df Make sure we have a legal type (and simple) before continuing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117848 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 21:25:26 +00:00
Benjamin Kramer
943beeb747 Validate HTML.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117847 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 21:07:28 +00:00
Chris Lattner
50e5972dc6 add missing tag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117846 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 20:21:00 +00:00
Chris Lattner
6fa152c8fb have GetAliasRequiredFeatures get its features from
AsmMatcherInfo so we don't have two places that know the
feature -> enum mapping.  No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117845 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 20:15:02 +00:00
Chris Lattner
0aed1e7701 simplify code that creates SubtargetFeatureInfo, ensuring that features
that are only used by MnemonicAliases will be found.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117844 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 20:07:57 +00:00
Chris Lattner
d7e409da6d fix a fixme in stringmatcher, having it generate nice looking code if the
'tomatch' code contains \n's.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117843 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 19:57:17 +00:00
Chris Lattner
8cf8bcc40c fix typos and some serious bugs in feature handling (but not for
cases that are currently exercised).  Thanks to Frits van Bommel for
the great review!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117840 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 19:47:49 +00:00
Chris Lattner
0f899c78e1 Resolve a terrible hack in tblgen: instead of hardcoding
"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117831 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 19:38:20 +00:00
Chris Lattner
693173feef Implement (and document!) support for MnemonicAlias's to have Requires
directives, allowing things like this:

def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;

Move the rest of the X86 MnemonicAliases over to the .td file.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117830 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 19:23:13 +00:00
Chris Lattner
8cc0a6b788 fix build problem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117828 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 18:57:07 +00:00
Chris Lattner
4fd32c6648 diagnose targets that define two alises with the same 'from' mnemonic
with a useful error message instead of having tblgen explode with an 
assert.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117827 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 18:56:12 +00:00
Chris Lattner
7fd4489de1 emit the mnemonic aliases in their own helper function instead of
inline into MatchInstructionImpl.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117826 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 18:48:18 +00:00