Craig Topper
d978c54e60
Use MVT instead of EVT as the argument to all the shuffle decode functions. Simplify some of the decode functions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156268 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-06 19:46:21 +00:00
Craig Topper
bdcbcb3ae7
Add VPERMQ/VPERMPD to the list of target specific shuffles that can be looked through for DAG combine purposes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156266 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-06 18:54:26 +00:00
Craig Topper
156f5bb56e
Add shuffle decode support for VPERMQ/VPERMPD.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156265 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-06 18:44:02 +00:00
Jim Grosbach
e5f31ad55e
Nuke a few dead remnants of the CBE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156241 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 17:45:12 +00:00
Benjamin Kramer
aaf723dd2b
Add a new target hook "predictableSelectIsExpensive".
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This will be used to determine whether it's profitable to turn a select into a
branch when the branch is likely to be predicted.
Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM.
I'm not entirely happy with the name of this flag, suggestions welcome ;)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156233 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05 12:49:14 +00:00
Preston Gurd
3d142e58ef
Adds Intel Atom scheduling latencies to X86InstrSystem.td.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156194 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 19:26:37 +00:00
Craig Topper
31a207a3b7
Fix some loops to match coding standards. No functional change intended.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156159 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 06:39:13 +00:00
Craig Topper
6643d9c180
Fix up some spacing. No functional change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156158 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 06:18:33 +00:00
Craig Topper
5da8a80377
Simplify broadcast lowering code. No functional change intended.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156157 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 05:49:51 +00:00
Craig Topper
f3640d7ec1
Allow v16i16 and v32i8 shuffles to be rewritten as narrower shuffles.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156156 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 04:44:49 +00:00
Craig Topper
11ac1f81a8
Simplify shuffle narrowing code a bit. No functional change intended.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156154 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 04:08:44 +00:00
Jakob Stoklund Olesen
338607ae0d
Remove the SubRegClasses field from RegisterClass descriptions.
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This information in now computed by TableGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156152 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 03:30:34 +00:00
Craig Topper
b607264550
Use 'unsigned' instead of 'int' in a few places dealing with counts of vector elements.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156060 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 07:26:59 +00:00
Craig Topper
6b28d356c5
Fix 256-bit vpshuflw and vpshufhw immediate encoding to handle undefs in the lower half correctly. Missed in r155982.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156059 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 07:12:59 +00:00
Preston Gurd
c0f0a93936
For Intel Atom, use ILP scheduling always, instead of ILP for 64 bit
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and Hybrid for 32 bit, since benchmarks show ILP scheduling is better
most of the time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 22:02:02 +00:00
Preston Gurd
79bbe855cd
Change the Intel Atom detection code to recognize
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Lincroft and Medfield.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156025 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 21:38:46 +00:00
Preston Gurd
95f0cf0438
This patch continues the work of adding instruction latencies for X86 Atom,
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by providing the latencies for the instructions in X86InstrFPStack.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155996 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 16:03:35 +00:00
Manman Ren
e2849851b2
Revert r155853
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The commit is intended to fix rdar://10961709.
But it is the root cause of PR12720.
Revert it for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155992 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 15:24:32 +00:00
Craig Topper
a9a568a79d
Add support for selecting AVX2 vpshuflw and vpshufhw. Add decoding support for AsmPrinter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155982 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 08:03:44 +00:00
Jakub Staszak
dca40aa911
Remove unneeded break.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155959 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 23:08:16 +00:00
Jakub Staszak
bf14860572
Remove trailing spaces.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155956 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 23:04:38 +00:00
Preston Gurd
66413b61f0
This patch marks the X86 floating point stack registers ST0-ST7 as reserved
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in order to avoid assertion failures in the register scavenger. The assertion
failures were “Bad machine code: Using an undefined physical register” and
“Bad machine code: MBB exits via unconditional fall-through but its successor
differs from its CFG successor!”.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155930 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 19:50:22 +00:00
Manman Ren
769ea2f93f
X86: optimization for max-like struct
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This patch will optimize the following cases on X86
(a > b) ? (a-b) : 0
(a >= b) ? (a-b) : 0
(b < a) ? (a-b) : 0
(b <= a) ? (a-b) : 0
FROM
movl %edi, %ecx
subl %esi, %ecx
cmpl %edi, %esi
movl $0, %eax
cmovll %ecx, %eax
TO
xorl %eax, %eax
subl %esi, %edi
cmovll %eax, %edi
movl %edi, %eax
rdar: 10734411
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155919 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 17:16:15 +00:00
Alexey Samsonov
d07d06ceef
X86: Use StackRegister instead of FrameRegister in getFrameIndexReference (to generate debug info for local variables) if stack needs realignment
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155917 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 15:16:06 +00:00
Bill Wendling
7c4ce30ea6
Change the PassManager from a reference to a pointer.
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The TargetPassManager's default constructor wants to initialize the PassManager
to 'null'. But it's illegal to bind a null reference to a null l-value. Make the
ivar a pointer instead.
PR12468
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 08:27:43 +00:00
Craig Topper
c80e7d2ea4
Allow BMI, AES, F16C, POPCNT, FMA3, and CLMUL to be detected on AMD processors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155899 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 07:10:32 +00:00
Craig Topper
e499cdf10c
Make XOP and FMA4 require SSE4A to match GCC behavior. Use this to simplify Bulldozer feature list.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155897 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 06:54:48 +00:00
Craig Topper
ff72e74d34
Attempt to handle MRMInitReg in emitVEXOpcodePrefix. Hopefully fixes PR12711.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155896 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 06:34:01 +00:00
Craig Topper
e106d2e2ac
Make XOP imply AVX as its needed to legalize the registers types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155891 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 05:41:41 +00:00
Craig Topper
c49c6e154a
Remove HasSSE2 from AES and CLMUL predicates. It's now implied by the HasAES and HasCLMUL predicates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155890 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 05:35:02 +00:00
Craig Topper
da1a984159
Make CLMUL and AES imply SSE2 since its needed to legalize the type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155888 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 05:28:32 +00:00
Craig Topper
ed39ac5026
Enable AVX and FMA4 for AMD Bulldozer processors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155885 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 05:18:13 +00:00
Manman Ren
16a76519a5
X86: optimization for -(x != 0)
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This patch will optimize -(x != 0) on X86
FROM
cmpl $0x01,%edi
sbbl %eax,%eax
notl %eax
TO
negl %edi
sbbl %eax %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155853 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30 22:51:25 +00:00
Chad Rosier
238ae31aa3
Tidy up. No functional change intended.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155832 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30 17:47:15 +00:00
Derek Schuff
ddc693bd22
Fix fastcc structure return with fast-isel on x86-32
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On x86-32, structure return via sret lets the callee pop the hidden
pointer argument off the stack, which the caller then re-pushes.
However if the calling convention is fastcc, then a register is used
instead, and the caller should not adjust the stack. This is
implemented with a check of IsTailCallConvention
X86TargetLowering::LowerCall but is now checked properly in
X86FastISel::DoSelectCall.
(this time, actually commit what was reviewed!)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155825 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30 16:57:15 +00:00
Craig Topper
7d1e3dcf71
No need to normalize index before calling Extract128BitVector
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155811 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30 05:17:10 +00:00
Pete Cooper
6942f706aa
Copied all the VEX prefix encoding code from X86MCCodeEmitter to the x86 JIT emitter. Needs some major refactoring as these two code emitters are almost identical
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155810 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30 03:56:44 +00:00
Jakub Staszak
6610b1db55
Remove unneeded casts. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155800 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-29 20:52:53 +00:00
Craig Topper
d77d2feb7a
Simplify code a bit. No functional change intended.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155798 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-29 20:22:05 +00:00
Derek Schuff
f3db6b855e
Revert r155745
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155746 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 23:37:41 +00:00
Derek Schuff
9dc28b0722
Fix fastcc structure return with fast-isel on x86-32
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On x86-32, structure return via sret lets the callee pop the hidden
pointer argument off the stack, which the caller then re-pushes.
However if the calling convention is fastcc, then a register is used
instead, and the caller should not adjust the stack. This is
implemented with a check of IsTailCallConvention
X86TargetLowering::LowerCall but is now checked properly in
X86FastISel::DoSelectCall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155745 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 23:27:17 +00:00
Craig Topper
66ddd153f6
Use 'unsigned' instead of 'int' in several places when retrieving number of vector elements.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155742 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 22:54:43 +00:00
Chad Rosier
a73b6fc511
Add x86-specific DAG combine to simplify:
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x == -y --> x+y == 0
x != -y --> x+y != 0
On x86, the generated code goes from
negl %esi
cmpl %esi, %edi
je .LBB0_2
to
addl %esi, %edi
je .L4
This case is correctly handled for ARM with "cmn".
Patch by Manman Ren.
rdar://11245199
PR12545
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155739 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 22:33:25 +00:00
Craig Topper
b4a8aef96d
Tidy up spacing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155733 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 21:05:09 +00:00
Benjamin Kramer
17c836c4b5
X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures.
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* Model FPSW (the FPU status word) as a register.
* Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions.
* During Legalize/Lowering, build a node sequence to transfer the comparison
result from FPSW into EFLAGS. If you're wondering about the right-shift: That's
an implicit sub-register extraction (%ax -> %ah) which is handled later on by
the instruction selector.
Fixes PR6679. Patch by Christoph Erhardt!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155704 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 12:07:43 +00:00
Preston Gurd
c573b1f7ae
Trivial change to set UseLeaForSP flag in addition to toggling
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the FeatureLeaForSP feature bit when llvm auto detects Intel Atom.
Patch by Andy Zhang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26 19:52:27 +00:00
Craig Topper
1203f2f138
Enable detection of AVX and AVX2 support through CPUID. Add AVX/AVX2 to corei7-avx, core-avx-i, and core-avx2 cpu names.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155618 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26 06:40:15 +00:00
Craig Topper
c16f851569
Use vector_shuffles instead of target specific unpack nodes for AVX ZERO_EXTEND/ANY_EXTEND combine. These will be converted to target specific nodes during lowering. This is more consistent with other code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155537 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25 06:39:39 +00:00
Nadav Rotem
7bc9698f3a
AVX: Add additional vbroadcast replacement sequences for integers.
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Remove the v2f64 patterns because it does not match any vbroadcast
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155461 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 18:09:59 +00:00
Nadav Rotem
87ffdbcb7b
AVX2: The BLENDPW instruction selects between vectors of v16i16 using an i8
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immediate. We can't use it here because the shuffle code does not check that
the lower part of the word is identical to the upper part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155440 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 11:27:53 +00:00