Benjamin Kramer
5eccf67492
Mips: Don't create a dangling IR function just to get the address of a symbol.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146340 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-11 12:21:34 +00:00
Nick Lewycky
ead7448a85
Also remove unnecessary includes from this file, which was supposed to be part
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of r146334!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146338 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-11 00:45:13 +00:00
Nick Lewycky
531bb82556
Minimize #include's and forward-declares in Target.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146335 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 22:35:47 +00:00
Nick Lewycky
b3ffe102fe
Refactor the implementation of the TargetOptions out of TargetMachine, taking
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the only parts of TM that depends on CodeGen headers with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146334 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 22:34:41 +00:00
Chad Rosier
4552d3e22a
[fast-isel] SelectInsertValue seems to be causing miscompiles for ARM. Disable while I investigate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146331 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 21:27:40 +00:00
Chad Rosier
d440f678fb
Revert r146322 to appease buildbots. Original commit message:
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Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for
FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second
attempt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146328 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 19:55:03 +00:00
Chad Rosier
b435aa2c1d
Typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146327 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 19:48:51 +00:00
Stepan Dyatkovskiy
8c0b807e8f
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 08:42:24 +00:00
Hal Finkel
fed4d19edd
Make CR spill and restore use a reserved register. These operations cannot use the register scavenger because the scavenger can only scavenge one register and frame-index elimination may have already grabbed it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146318 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 04:50:53 +00:00
Jakob Stoklund Olesen
77caaf0fc0
Try to align the point where a large basic block is split.
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The split point is picked such that the newly created water has the same
alignment as the function. This makes the island suitable for constant
pool entries with potentially higher alignment.
This also fixes an issue where the basic block was split one instruction
too late, causing nonconvergence of the algorithm.
<rdar://problem/10550705>
There is still an issue with correctly packing differently aligned
entries in the island.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146314 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 02:55:10 +00:00
Jakob Stoklund Olesen
2d5023bbcf
More debug output formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146313 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 02:55:06 +00:00
Rafael Espindola
f3aefb56de
Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gas
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does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146311 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 02:28:43 +00:00
Andrew Trick
fa1948a40f
LSR: ignore strides in outer loops.
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Since we're not rewriting IVs in other loops, there's not much reason
to consider their stride when generating formulae.
This should reduce the number of useless formulas considered by LSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146302 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 00:25:00 +00:00
Jim Grosbach
48171e7fbe
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146300 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-10 00:01:02 +00:00
Eli Friedman
effab8fa24
Splats can contain undef's; make sure to handle them correctly. PR11526.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146299 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 23:54:42 +00:00
Jim Grosbach
21d7fb814a
ARM add some pre-UAL VFP mnemonics for convenience when porting old code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146296 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 23:34:09 +00:00
Bill Wendling
f4374e46fd
Add dump method for debugging.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 23:18:34 +00:00
Jim Grosbach
8a12e3b5df
ARM allows '' syntax, not just '#imm' for assembly.
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Backwards compatibility with 'gas'. #imm is the preferered and documented
syntax, but lots of existing code uses the '$' prefix, so we should
support it if we can.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146285 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 22:25:03 +00:00
Kostya Serebryany
25a8b809a0
[asan] call __asan_init from .preinit_array. This simplifies __asan_init vs malloc chicken-and-egg situation on Android and probably on other flavours of Linux. Patch by eugenis@google.com.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146284 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 22:09:32 +00:00
Jim Grosbach
840bf7eda7
ARM assembly aliases for BIC<-->AND (immediate).
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When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.
rdar://10550057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 22:02:17 +00:00
Jim Grosbach
4332983e77
ARM NEON data type aliases for VBIC(register).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146281 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 21:46:04 +00:00
Jim Grosbach
a4e3c7fc4b
ARM assembly parsing and encoding for VLD2 with writeback.
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Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 21:28:25 +00:00
Jakub Staszak
2fac1d5d61
SplitBlockPredecessors uses ArrayRef instead of Data and Size.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146277 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 21:19:53 +00:00
Chad Rosier
cd462d055f
[fast-isel] Add support for selecting insertvalue.
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rdar://10530851
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146276 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 20:09:54 +00:00
Rafael Espindola
3c68acd202
Handle reloc_signed_4byte in here. Not doing so was a regression from my
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previous commit. It is strange that we see it in 32 bits. We already
have a fixme about it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146273 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 19:57:29 +00:00
Jakob Stoklund Olesen
493ad6b95d
User a helper overload for a common pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146270 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 19:44:39 +00:00
Jim Grosbach
2af50d981d
Tidy up. Better base class factoring.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146267 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 19:07:20 +00:00
Jim Grosbach
1f94ec7b59
Tidy up. Better base class factoring.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146266 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 18:54:11 +00:00
Jakob Stoklund Olesen
3c4615eef2
Tweak debugging output.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146264 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 18:20:35 +00:00
Kevin Enderby
94c2e85bea
The second part of support for generating dwarf for assembly source files. This
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generates the dwarf Compile Unit DIE and a dwarf subprogram DIE for each
non-temporary label.
The next part will be to get the clang driver to enable this when assembling
a .s file. rdar://9275556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146262 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 18:09:40 +00:00
Benjamin Kramer
bf67a99c35
This is now implemented.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146258 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 15:45:57 +00:00
Benjamin Kramer
b653397dcd
X86: Add patterns for the various rounding ops for SSE4.1 and AVX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146257 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 15:44:03 +00:00
Benjamin Kramer
a73fb9adbb
X86: Split (v)rounds[sd] into a normal and an intrinsic version.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146256 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 15:43:55 +00:00
Evan Cheng
32f9763017
Move isUnpredicatedTerminator() default implementation to TargetInstrInfoImpl to break Target's dependency on CodeGen.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146247 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 06:41:08 +00:00
Evan Cheng
85abb2700d
Remove hasSSE1orAVX(). It's the same as hasXMM().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146246 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 06:32:46 +00:00
Andrew Trick
5d73448bb7
Add -unroll-runtime for unrolling loops with run-time trip counts.
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Patch by Brendon Cahoon!
This extends the existing LoopUnroll and LoopUnrollPass. Brendon
measured no regressions in the llvm test suite with -unroll-runtime
enabled. This implementation works by using the existing loop
unrolling code to unroll the loop by a power-of-two (default 8). It
generates an if-then-else sequence of code prior to the loop to
execute the extra iterations before entering the unrolled loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 06:19:40 +00:00
Rafael Espindola
1d5969d839
Handle the case of the magical _GLOBAL_OFFSET_TABLE_ showing up in a
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symbol difference. This matches gas behavior and fixes PR11513.
We still don't handle _GLOBAL_OFFSET_TABLE_ in data sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146238 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 03:03:58 +00:00
Akira Hatanaka
6df7e23f0c
Rename WrapperPIC. It is now used for both pic and static.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146232 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 01:53:17 +00:00
Akira Hatanaka
0dca9456c5
jalr should use t9 ($25) for indirect calls regardless of the relocation model
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specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146229 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 01:45:12 +00:00
Devang Patel
f5b9a74f0a
Fix comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146226 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 01:25:04 +00:00
Devang Patel
2b1d77355b
Update stale comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146220 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 01:18:48 +00:00
Eli Friedman
2dd0353fec
Fix a couple of logic bugs in TargetLowering::SimplifyDemandedBits. PR11514.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146219 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 01:16:26 +00:00
Devang Patel
7f7f0902a6
Revert r146184. I am seeing performance regression cause by this patch in one test case.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146205 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 23:52:00 +00:00
Jim Grosbach
976c0da213
ARM convenience aliases for VSQRT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146201 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:51:25 +00:00
Michael J. Spencer
a81ac8f2b5
Support/FileSystem: Implement recursive_directory_iterator and make
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directory_iterator preserve InputIterator semantics on copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146200 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:50:09 +00:00
Nick Lewycky
c9b98ad7a7
Fix infinite loop in DSE when deleting a free in a reachable loop that's also
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trivially infinite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146197 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:36:35 +00:00
Evan Cheng
e955726a0e
Add 256-bit variant vmovss and vmovsd patterns. rdar://10538417
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146196 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:30:45 +00:00
Jim Grosbach
8759c3f548
ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146194 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:19:04 +00:00
Owen Anderson
243eb9ecbb
Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter can use the former to prevent the formation of libm SDNode's when -fno-builtin is passed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146193 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:15:21 +00:00
Jim Grosbach
6b044c2609
ARM VSHR implied destination operand form aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:06:06 +00:00
Evan Cheng
13d2ba34f2
Add various missing AVX patterns which was causing crashes. Sadly, the generated
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code looks pretty bad compared to SSE.
rdar://10538793
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146191 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:05:28 +00:00
Devang Patel
e265bcf1a6
Refactor. No intentional functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146187 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 21:48:01 +00:00
Chad Rosier
73e08d3507
Add rather verbose stats for fast-isel failures.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146186 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 21:37:10 +00:00
Jim Grosbach
a62d11ea94
ARM asm parser, just issue a warning for a duplicate reg in a list.
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For better 'gas' compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146185 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 21:34:20 +00:00
Devang Patel
cf405ba7a6
Filter "sink to" candidate blocks sooner. This avoids unnecessary computation to determine whether the block dominates all uses or not.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 21:33:23 +00:00
Akira Hatanaka
7a7194b529
Pass a GlobalAddress instead of an ExternalSymbol to LowerCallTo in
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MipsTargetLowering::LowerGlobalTLSAddress. This is necessary to have
call16(__tls_get_addr) emitted instead of got_disp(__tls_get_addr) when the
target is Mips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146183 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 21:05:38 +00:00
Jim Grosbach
120313435d
ARM VSUB implied destination operand form aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146182 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:56:26 +00:00
Owen Anderson
587e34065f
Don't explicitly marked libm rounding ops as legal on SSE4.1/AVX. There don't seem to be patterns for these, so I don't know why they were marked legal in the first place.
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Fixes failures caused by r146171.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146180 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:51:38 +00:00
Jim Grosbach
9e7b42a40e
ARM VQADD implied destination operand form aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:49:43 +00:00
Jim Grosbach
1c2c8a9389
ARM a few more VMUL implied destination operand form aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146177 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:42:35 +00:00
Akira Hatanaka
ca0747917d
Implement 64-bit support for thread local storage handling.
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- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC.
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
substituted with other existing nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146175 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:34:32 +00:00
Owen Anderson
4a4fdf3476
Teach SelectionDAG to match more calls to libm functions onto existing SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 19:32:14 +00:00
Jim Grosbach
40e2855547
ARM assembler support for register name aliases.
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rdar://10550084
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 19:27:38 +00:00
Evan Cheng
43d5d4ca1c
Make MachineInstr instruction property queries more flexible. This change all
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clients to decide whether to look inside bundled instructions and whether
the query should return true if any / all bundled instructions have the
queried property.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146168 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 19:23:10 +00:00
Evan Cheng
2f435511e9
Many of the SSE patterns should not be selected when AVX is available. This led to the following code in X86Subtarget.cpp
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if (HasAVX)
X86SSELevel = NoMMXSSE;
This is so patterns that are predicated on hasSSE3, etc. would not be selected when avx is available. Instead, the AVX variant is selected.
However, this breaks instructions which do not have AVX variants.
The right way to fix this is for the SSE but not-AVX patterns to predicate on something like hasSSE3() && !hasAVX().
Then we can take out the hack in X86Subtarget.cpp. Patterns which do not have AVX variants do not need to change.
However, we need to audit all the patterns before we make the change. This patch is workaround that fixes one specific case,
the prefetch instructions. rdar://10538297
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 19:00:42 +00:00
Daniel Dunbar
3b0887e291
Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics
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sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146157 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 17:32:18 +00:00
Jan Sjödin
703420f50e
Src2 and src3 were accidentally swapped for the FMA4 rr patterns. Undo this and fix the encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146151 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 14:43:19 +00:00
Nadav Rotem
44bac7cd65
Fix a bug in the integer-promotion of bitcast operations on vector types.
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We must not issue a bitcast operation for integer-promotion of vector types, because the
location of the values in the vector may be different.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146150 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 13:10:01 +00:00
Stepan Dyatkovskiy
72590c9738
Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146143 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 07:55:03 +00:00
Hal Finkel
6772452644
MTCTR needs to be glued to BCTR so that CTR is not marked dead in MTCTR (another find by -verify-machineinstrs)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146137 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 04:36:44 +00:00
Pete Cooper
8f391d9330
Reverting r145899 as it breaks clang self-hosting
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146136 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 03:24:10 +00:00
Jim Grosbach
730fe6c1b6
ARM NEON two-operand aliases for VSHL(immediate).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 01:30:04 +00:00
Jakob Stoklund Olesen
e6f9e9d836
Drop the HasInlineAsm flag.
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It is not used any more. We are tracking inline assembly misalignments
directly through the BBInfo.Unalign and KnownBits fields.
A simple conservative size estimate is not good enough since it can
cause alignment padding to be underestimated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146124 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 01:22:39 +00:00
Jim Grosbach
ff4cbb4c9a
ARM NEON two-operand aliases for VSHL(register).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146123 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 01:12:35 +00:00
Jakob Stoklund Olesen
99486be8ba
Simplify offset verification.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146121 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 01:10:05 +00:00
Jim Grosbach
517a013a4f
Fix copy/past-o.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146120 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 01:02:26 +00:00
Jim Grosbach
2b8810c500
ARM NEON two-operand aliases for VMUL.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146119 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:59:47 +00:00
Jakob Stoklund Olesen
540c6d9d26
Don't include alignment padding in BBInfo.Size.
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Compute alignment padding before and after basic blocks dynamically.
Heed basic block alignment.
This simplifies bookkeeping because we don't have to constantly add and
remove padding from BBInfo.Size. It also makes it possible to track the
extra known alignment bits we get after a tBR_JTr terminator and when
entering an aligned basic block.
This makes the ARMConstantIslandPass aware of aligned basic blocks.
It is tricky to model block alignment correctly when dealing with inline
assembly and tBR_JTr instructions that have variable size. If inline
assembly turns out to be smaller than expected, that may cause following
alignment padding to be larger than expected. This could cause constant
pool entries to move out of range.
To avoid that problem, we use the worst case alignment padding following
inline assembly. This may cause slightly suboptimal constant island
placement in aligned basic blocks following inline assembly. Normal
functions should be unaffected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146118 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:55:02 +00:00
Jim Grosbach
8254f02231
ARM VFP support 'fmrs/fmsr' aliases for 'vldr'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146116 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:52:55 +00:00
Jim Grosbach
67ca1adf82
ARM VFP support 'flds/fldd' aliases for 'vldr'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146115 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:49:29 +00:00
Jim Grosbach
a44f2c4a28
ARM optional destination operand variants for VEXT instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146114 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:43:47 +00:00
Chad Rosier
667f826622
Fix 80-column.
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Simplify code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146112 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:38:45 +00:00
Jim Grosbach
3bc8a3d3af
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146111 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:31:07 +00:00
Chad Rosier
14d622dce6
Fix comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146109 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:11:31 +00:00
Peter Collingbourne
d40e103ea5
EngineBuilder: support for custom TargetOptions. Fixes the
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ExceptionDemo example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146108 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:58:57 +00:00
Chad Rosier
0c89f7fda2
Fix comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146107 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:57:55 +00:00
Jim Grosbach
af4edea67b
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
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For 'gas' compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:40:58 +00:00
Akira Hatanaka
08a7d92da6
Modify class ReadHardware and add definition of 64-bit version of instruction
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RDHWR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146101 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:31:26 +00:00
Akira Hatanaka
f99c1e5a19
Add newline.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146100 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:26:03 +00:00
Akira Hatanaka
be7b67368c
Add 64-bit HWR29 register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:23:52 +00:00
Akira Hatanaka
da86fa14f0
32 to 64-bit anyext pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146097 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:21:19 +00:00
Akira Hatanaka
0a18cdc372
32 to 64-bit zext pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146096 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:14:41 +00:00
Jim Grosbach
9fa0a743e6
ARM two-operand aliases for VAND/VEOR/VORR instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146095 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:08:12 +00:00
Jim Grosbach
30a264eb7f
ARM two-operand aliases for VADDW instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146093 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:01:10 +00:00
Jim Grosbach
d900441e13
ARM two-operand aliases for VADD instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146091 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 22:52:54 +00:00
Chad Rosier
32c5981005
Flesh out a bit more of the bitcode use-list ordering preservation code.
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Nothing too interesting at this point, but comments are welcome.
Part of rdar://9860654 and PR5680.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146090 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 22:49:05 +00:00
Bruno Cardoso Lopes
d1bcf0dbc1
Variable cleanup. Based on past patch submittals variable names have
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been normalized and more descriptive comments added. Patch by Reed
Kotler and Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146088 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 22:35:30 +00:00
Eli Friedman
0e6307f642
Make sure we correctly set LiveRegGens when a call is unscheduled. <rdar://problem/10460321>. No testcase because this is very sensitive to scheduling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146087 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 22:24:28 +00:00
Akira Hatanaka
2c78be01f6
64-bit WrapperPICPat patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146086 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 22:11:43 +00:00
Eli Friedman
30c44e18bf
Fix an assertion in the scheduler. PR11386. No testcase included because it's rather delicate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146083 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 22:06:02 +00:00
Akira Hatanaka
20aa12ae5c
Define base class for WrapperPICPat.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146081 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 21:54:54 +00:00
Akira Hatanaka
7398bf01c2
Modify LowerFCOPYSIGN to handle Mips64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146080 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 21:48:50 +00:00
Chad Rosier
cbbb09687f
Begin adding experimental support for preserving use-list ordering of bitcode
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files. First, add a new block USELIST_BLOCK to the bitcode format. This is
where USELIST_CODE_ENTRYs will be stored. The format of the USELIST_CODE_ENTRYs
have not yet been defined. Add support in the BitcodeReader for parsing the
USELIST_BLOCK.
Part of rdar://9860654 and PR5680.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146078 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 21:44:12 +00:00
Nick Lewycky
e77ae2d692
These global variables aren't thread-safe, STATISTIC is. Andy Trick tells me
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that he isn't using these any more, so just delete them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146076 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 21:35:59 +00:00
Chad Rosier
4e6c03fc3d
ValueEnumerator - debug dump().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146070 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 20:44:46 +00:00
Akira Hatanaka
bd15090aa2
Fix comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 20:15:01 +00:00
Akira Hatanaka
3bdc03a592
Fix comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146062 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 20:13:53 +00:00
Akira Hatanaka
4d0eb637f0
Fix 64-bit immediate patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 20:10:24 +00:00
Jim Grosbach
4f66a050a2
Nuke inadvertant debugging commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146057 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 19:56:16 +00:00
Jim Grosbach
577b09155f
Darwin assembler improved relocs when w/o subsections_via_symbols.
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When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146054 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 19:46:59 +00:00
Jakub Staszak
feb468ab24
Remove unneeded semicolon.
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Skip two looking up at BlockChain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146053 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 19:46:10 +00:00
Jim Grosbach
8524bca750
Thumb2 alias for long-form pop and friends.
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rdar://10542474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 18:32:28 +00:00
Jim Grosbach
9a70df99ca
ARM support the .arm and .thumb directives for assembly mode switching.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146042 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 18:04:19 +00:00
Jim Grosbach
470855b24f
ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146039 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 17:51:15 +00:00
Duncan Sands
0ea3a0c236
Remove unused include.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146037 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 17:18:31 +00:00
Craig Topper
d802326335
Fix a bunch of SSE/AVX patterns to use proper memop types. In particular, not using integer loads other than v2i64/v4i64 since the others are all promoted.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146031 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 08:30:53 +00:00
Bill Wendling
b3ec329c14
Adjust the stack by one pointer size for all frameless stacks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146030 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 07:58:55 +00:00
Bill Wendling
c61751373a
Fix off-by-one error when encoding the stack size for a frameless stack.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146029 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 07:49:49 +00:00
Evan Cheng
5a96b3dad2
Add bundle aware API for querying instruction properties and switch the code
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generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 07:15:52 +00:00
David Blaikie
5729c5848c
Adding missing anchor to DATDeltaAlgorithm.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146025 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 06:44:23 +00:00
Hal Finkel
234bb38d6c
make CR spill and restore 64-bit clean (no functional change), and fix some other problems found with -verify-machineinstrs
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 06:34:06 +00:00
Hal Finkel
6d0e014b1f
make base register selection used in eliminateFrameIndex 64-bit clean
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146023 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 06:34:02 +00:00
Hal Finkel
ae37cd0a37
set mayStore and mayLoad on CR pseudos
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 06:33:57 +00:00
Hal Finkel
7ad6b7d359
64-bit LR8 load should use X11 not R11
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 06:32:37 +00:00
Jakob Stoklund Olesen
2fe71c5ef4
Eliminate delta argument from AdjustBBOffsetsAfter.
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The block offset can be computed from the previous block. That is more
robust than keeping track of a delta.
Eliminate one redundant AdjustBBOffsetsAfter call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146018 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 05:17:30 +00:00
Jakob Stoklund Olesen
a26811ec83
Compute some alignment information for each basic block.
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These fields are not used for anything yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146017 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 04:17:35 +00:00
Eli Friedman
1c663fee56
Zap unnecessary isIntDivCheap() check. PR11485. No testcase because this doesn't affect any in-tree target.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146015 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 03:55:52 +00:00
Jim Grosbach
1ceef1a491
ARM tidy up and remove no longer needed InstAlias definitions.
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The TokenAlias handling of data type suffices renders these unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146010 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:50:36 +00:00
Jakob Stoklund Olesen
5bb32530bc
Move common expression into a method.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146008 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:22:52 +00:00
Jim Grosbach
9f3d220c63
ARM Implement ARM ARM Table A7-3 via TokenAlias.
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Data type suffix aliasing. Previously handled via lots of instruction
aliases. Cleanup of those forthcoming.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146007 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:17:58 +00:00
Jakob Stoklund Olesen
a3f331bd81
Group BBSizes and BBOffsets into a single vector<BasicBlockInfo>.
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No functional change is intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146005 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:08:25 +00:00
Jakob Stoklund Olesen
0400345198
Add missing check.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:08:22 +00:00
Jim Grosbach
3b8991cc98
ARM: NEON SHLL instruction immediate operand range checking.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:07:24 +00:00
Eli Friedman
f91abd22be
Support vector bitcasts in the AsmPrinter. PR11495.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146001 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 00:50:54 +00:00
Bruno Cardoso Lopes
e3d3572e28
Add a few moreLocal/Global R_MIPS_GOT related fixups and
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make the addend fixup code a bit more generic
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145998 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 00:28:57 +00:00
Jakob Stoklund Olesen
2068215e85
Add MachineOperand IsInternalRead flag.
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This flag is used when bundling machine instructions. It indicates
whether the operand reads a value defined inside or outside its bundle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 00:22:07 +00:00
Eli Friedman
26323442d5
Fix an optimization involving EXTRACT_SUBVECTOR in DAGCombine so it behaves correctly. PR11494.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145996 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 00:11:56 +00:00
Jakub Staszak
c9040b3b13
Remove unneeded type.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145995 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 00:08:00 +00:00
Jim Grosbach
4e4139588c
ARM: Parameterize the immediate operand type for NEON VSHLL.
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No functional change yet. Will be implementing range-checked immediates
for better diagnostics and disambiguation of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145994 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 00:02:17 +00:00
Jakub Staszak
e6d81ad6a5
- Remove unneeded #includes.
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- Remove unused types/fields.
- Add some constantness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145993 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 23:59:33 +00:00
Jakob Stoklund Olesen
6fbea43b0b
Revert r145971: "Use conservative size estimate for tBR_JTr."
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This caused more offset errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145980 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 22:41:31 +00:00
Bill Wendling
054a8be154
Re-enable compact unwind. It seems to work now. <rdar://problem/10441838>
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145977 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 22:18:12 +00:00
Bill Wendling
84d518af19
Explicitly check for the different SUB instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145976 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 22:14:27 +00:00
Evan Cheng
7c2a4a30e0
First chunk of MachineInstr bundle support.
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1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 22:12:01 +00:00
Jakob Stoklund Olesen
d25c27807e
Use conservative size estimate for tBR_JTr.
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This pseudo-instruction contains a .align directive in its expansion, so
the total size may vary by 2 bytes.
It is too difficult to accurately keep track of this alignment
directive, just use the worst-case size instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145971 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 21:55:39 +00:00
Jakob Stoklund Olesen
305e5fe797
Remove alignment from deserted constant islands.
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ARMConstantIslandPass may sometimes leave empty constant islands behind
(it really shouldn't). Remove the alignment from the empty islands so
the size calculations are still correct.
This should fix the many Thumb1 assembler errors in the nightly test
suite.
The reduced test case for this problem is way too big. That is to be
expected for ARMConstantIslandPass bugs.
<rdar://problem/10534709>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145970 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 21:55:35 +00:00
Bill Wendling
581ac2723c
Encode the total stack if there isn't a frame.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 21:34:01 +00:00
Bill Wendling
57a3cd2f32
* Add a macro to remove a magic number.
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* Rename variables to reflect what they're actually used for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145968 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 21:23:42 +00:00
Jakob Stoklund Olesen
f2e944523c
Pretty-print basic block alignment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145965 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 21:08:39 +00:00
Hal Finkel
d21e930eac
add RESTORE_CR and support CR unspills
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145961 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 20:55:36 +00:00