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5897 Commits

Author SHA1 Message Date
Eli Friedman
dca62d53b7 Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141585 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 22:28:47 +00:00
Devang Patel
6b50bc9d88 If loop header is also loop exiting block then it may not be safe to hoist instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141576 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 20:32:03 +00:00
Nadav Rotem
a7934dd8e4 Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the 
instruction set has no 64-bit SRA support.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141570 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 19:31:45 +00:00
Devang Patel
9ac743a4ee Add dominance check for the instruction being hoisted. 
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141569 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 19:09:20 +00:00
Benjamin Kramer
a86a58695d X86: Add patterns for the movbe instruction (mov + bswap, only available on atom) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141563 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 18:34:56 +00:00
Bill Wendling
eba564ceac Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to 
hang, and possibly SPEC/CINT2006/464_h264ref.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141560 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 18:27:30 +00:00
Bill Wendling
8129d21396 When getting the number of bits necessary for addressing mode 
ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141529 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-10 07:24:23 +00:00
Jakob Stoklund Olesen
ed74482704 Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies. 
In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.

TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.

This fixes PR11088.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141499 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-08 18:28:28 +00:00
Jakob Stoklund Olesen
a55f6575ae Add missing test case for r141410. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141498 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-08 18:06:54 +00:00
Evan Cheng
7c1780c5fe High bits of movmskp{s|d} and pmovmskb are known zero. rdar://10247336 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141371 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 17:21:44 +00:00
Bob Wilson
6d2f9cec71 Reenable tail calls for iOS 5.0 and later. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141370 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 17:17:49 +00:00
Bob Wilson
2fef4573df Reenable use of divmod compiler_rt functions for iOS 5.0 and later. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141368 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 16:59:21 +00:00
Anton Korobeynikov
244455e6d6 Peephole optimization for ABS on ARM. 
Patch by Ana Pazos!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141365 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-07 16:15:08 +00:00
Cameron Zwarich
d78ebe1e12 Remove a check from ARM shifted operand isel helper methods, which were blocking 
merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141247 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 23:38:50 +00:00
Dan Gohman
da5836572d Make this test less sensitive to codegen optimizations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141195 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-05 18:13:08 +00:00
Akira Hatanaka
bbb47b320d Move CHECK after entry label. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141030 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:24:30 +00:00
Akira Hatanaka
43e43f7d8b Add support for 64-bit logical NOR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141029 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:23:18 +00:00
Akira Hatanaka
2d57088ff0 Add support for 64-bit count leading ones and zeros instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141028 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:16:50 +00:00
Akira Hatanaka
dda4a07cd8 Add support for 64-bit divide instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141024 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:06:13 +00:00
Akira Hatanaka
04d3762ff1 Add support for 64-bit integer multiply instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141017 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 20:01:11 +00:00
Bill Wendling
0676d2a04c Filecheck-ize. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140904 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 23:40:29 +00:00
Bill Wendling
127f410c3a Add new line at end of file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140903 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 23:21:11 +00:00
Bill Wendling
e09b2a0d49 When inferring the pointer alignment, if the global doesn't have an initializer 
and the alignment is 0 (i.e., it's defined globally in one file and declared in
another file) it could get an alignment which is larger than the ABI allows for
that type, resulting in aligned moves being used for unaligned loads.

For instance, in file A.c:

   struct S s;

In file B.c:
   struct {
     // something long
   };
   extern S s;

   void foo() {
     struct S p = s;
     // ...
   }

this copy is a 'memcpy' which is turned into a series of 'movaps' instructions
on X86. But this is wrong, because 'struct S' has alignment of 4, not 16.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140902 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 23:19:55 +00:00
Akira Hatanaka
5773fd52ef Remove unnecessary checking of register operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140872 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 19:18:24 +00:00
Akira Hatanaka
c7bafe9241 Add definitions of Mips64 rotate instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140870 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 18:51:46 +00:00
Jim Grosbach
6f09fcf5da ARM Darwin default relocation model is PIC. 
This matches clang, so default options in llc and friends are now closer to
clang's defaults.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140863 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 17:41:35 +00:00
Akira Hatanaka
d80c13bfed Check values of immediate operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140860 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 17:19:21 +00:00
Akira Hatanaka
25a7d94e81 Mips64 shift instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140841 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 03:18:46 +00:00
Akira Hatanaka
f549ab7853 Mips64 arithmetic and logical instructions with one source register and 
immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140839 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 02:08:54 +00:00
Akira Hatanaka
a3defb07a0 Fill delay slot with useful instructions. Modified from Sparc's version of delay 
slot filler.

Patch by Reed Kotler at Mips Technologies.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140825 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 23:52:13 +00:00
Akira Hatanaka
c0be26909f Mips64 arithmetic and logical instructions with two source registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140806 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 20:37:56 +00:00
Andrew Trick
0c01bc385a LSR: rewrite inner loops only. 
Rewriting the entire loop nest now requires -enable-lsr-nested.
See PR11035 for some performance data.
A few unit tests specifically test nested LSR, and are now under a flag.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140762 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 01:33:38 +00:00
Andrew Trick
03b08764d2 whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140761 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 01:31:48 +00:00
Justin Holewinski
d57c1bc0b6 PTX: Add new patterns for bitconvert and any_extend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140753 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 01:13:12 +00:00
Evan Cheng
9b88d2d782 Tighten a ARM dag combine condition to avoid an identity transformation, which 
ends up introducing a cycle in the DAG.

rdar://10196296


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140733 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 23:16:31 +00:00
Eli Friedman
7d3e2b78c7 PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU does not support them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140723 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 21:00:25 +00:00
Justin Holewinski
d8e4ed2686 PTX: MC-ize the PTX back-end (patch 1 of N) 
Lay some groundwork for converting to MC-based asm printer. This is the first
of probably many patches to bring the back-end back up-to-date with all of the
recent MC changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140697 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-28 14:32:04 +00:00
Jakob Stoklund Olesen
df4b35e3dd Remove X86-dependent stuff from SSEDomainFix. 
This also enables domain swizzling for AVX code which required a few
trivial test changes.

The pass will be moved to lib/CodeGen shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140659 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 23:50:46 +00:00
Justin Holewinski
13e0c805a2 PTX: Add support for sitofp in backend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140593 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 01:04:47 +00:00
Eli Friedman
139e6699c4 Last batch of test conversions to new atomic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140585 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-27 00:17:29 +00:00
Eli Friedman
184944acdf Convert a bunch more tests over to the new atomic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140582 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 23:15:09 +00:00
Eli Friedman
47d3ee559a Convert more tests to new atomic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140567 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 21:36:10 +00:00
Eli Friedman
de412c391b Convert more tests over to the new atomic instructions. 
I did not convert Atomics-32.ll and Atomics-64.ll by hand; the diff is autoupgrade output.

The wmb test is gone because there isn't any way to express wmb with the new atomic instructions; if someone really needs a non-asm way to write a wmb on Alpha, a platform-specific intrisic could be added.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140566 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 21:30:17 +00:00
Eli Friedman
ad2d46d0a5 Convert more tests over to the new atomic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140559 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 20:27:49 +00:00
Justin Holewinski
63602ed876 PTX: Fix detection of stack load/store vs. global load/store, as well as fix the 
printing of local offsets

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140547 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 18:57:22 +00:00
Justin Holewinski
6272c5d874 PTX: Add .align tests to stack object test file 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140537 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 16:20:38 +00:00
Justin Holewinski
58788503b8 PTX: Fix some lingering issues with stack allocation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140535 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 16:20:34 +00:00
Justin Holewinski
c1d8fbd41a PTX: Unify handling of loads/stores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140533 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 16:20:28 +00:00
David Meyer
6b97870746 Only run tests in test/CodeGen/CBackend/X86 when both X86 and CBackend are supported 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140517 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 06:44:27 +00:00
David Meyer
8f418b11d2 PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140516 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 06:13:20 +00:00