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4462 Commits

Author SHA1 Message Date
Evan Cheng
75b41f1540 Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That 
is, it assumes addresses are 64-bit aligned (which should be the more common
case). If the alignment is found not to be aligned, then getOperandLatency()
would adjust the operand latency computation by one to compensate for it.
rdar://9294833


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129742 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-19 01:21:49 +00:00
Evan Cheng
b58a340fa2 Do not lose mem_operands while lowering VLD / VST intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129738 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-19 00:04:03 +00:00
Jim Grosbach
0d062c1e14 Trim a few unneeded includes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129723 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-18 21:35:54 +00:00
Sean Callanan
f6d9109124 Small fix to the ARM AsmParser to ensure that a 
superclass variable is instantiated properly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129713 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-18 20:20:44 +00:00
Stuart Hastings
c5eecbc4ec Correct result when a branch condition is live across a block 
boundary.  <rdar://problem/8933028>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129634 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-16 03:31:26 +00:00
Johnny Chen
3a96122c4a Thumb2 BFC was insufficiently encoded. 
rdar://problem/9292717


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129619 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 22:52:15 +00:00
Johnny Chen
a704bc9354 A8.6.315 VLD3 (single 3-element structure to all lanes) 
The a bit must be encoded as 0.

rdar://problem/9292625


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129618 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 22:49:08 +00:00
Cameron Zwarich
0cb11ac32f Add ORR and EOR to the CMP peephole optimizer. It's hard to get isel to generate 
a case involving EOR, so I only added a test for ORR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129610 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 21:24:38 +00:00
Cameron Zwarich
b485de5d8c The AND instruction leaves the V flag unmodified, so it falls victim to the same 
problem as all of the other instructions we fold with CMPs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129602 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 20:45:00 +00:00
Cameron Zwarich
ca3f6a3925 Add missing register forms of instructions to the ARM CMP-folding code. This 
fixes <rdar://problem/9287901>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129599 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 20:28:28 +00:00
Chris Lattner
7a2bdde0a0 Fix a ton of comment typos found by codespell. Patch by 
Luis Felipe Strano Moraes!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 05:18:47 +00:00
Evan Cheng
9eec66e604 Fix another fcopysign lowering bug. If src is f64 and destination is f32, don't 
forget to right shift the source by 32 first. rdar://9287902


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129556 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 01:31:00 +00:00
Johnny Chen
188ce9c78b For t2BFI, both Inst{26} and Inst{5} "should" be 0. 
Ref: I.1 Instruction encoding diagrams and pseudocode


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129552 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 00:35:08 +00:00
Johnny Chen
de29a52940 The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions 
(single element or n-element structure to all lanes).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129550 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 00:10:45 +00:00
Evan Cheng
06b2a60ef9 Follow up on r127913. Fix Thumb revsh isel. rdar://9286766 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129548 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-14 23:27:44 +00:00
Johnny Chen
cd695fdac1 Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129531 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-14 19:13:28 +00:00
Johnny Chen
e8d087ad35 Thumb disassembler did not handle tBRIND (indirect branch) properly. 
rdar://problem/9280370


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129480 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 21:59:01 +00:00
Johnny Chen
6c7e4147dc Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc). 
rdar://problem/9280470


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129471 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 21:35:49 +00:00
Johnny Chen
471d73d5d3 The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt. 
rdar://problem/9279440


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129469 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 21:04:32 +00:00
Cameron Zwarich
5af60ce2a8 Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129468 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 21:01:19 +00:00
Johnny Chen
9bb386a933 Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such. 
rdar://problem/9276651


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129462 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 19:46:05 +00:00
Johnny Chen
119af20c7b Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not properly handled. 
rdar://problem/9276427


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129456 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 17:51:02 +00:00
Johnny Chen
6e3ccc3c85 Forgot to add this change for http://llvm.org/viewvc/llvm-project?view=rev&revision=129387. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129451 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 16:56:08 +00:00
Cameron Zwarich
5876db7a66 Fix a typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129429 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 06:39:16 +00:00
Johnny Chen
55e6419b12 Add sanity check for Ld/St Dual forms of Thumb2 instructions. 
rdar://problem/9273947


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129411 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 23:31:00 +00:00
Jakob Stoklund Olesen
836a7de159 Add @earlyclobber constraints to the writeback register of all ARM store instructions. 
The ARMARM specifies these instructions as unpredictable when storing the
writeback register. This shouldn't affect code generation much since storing a
pointer to itself is quite rare.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129409 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 23:27:48 +00:00
Johnny Chen
ec51a6225c The Thumb2 RFE instructions need to have their second halfword fully specified. 
In addition, the base register is not rGPR, but GPR with th exception that:

    if n == 15 then UNPREDICTABLE

rdar://problem/9273836


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129391 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 21:41:51 +00:00
Johnny Chen
32cefad4b3 Add bad register checks for Thumb2 Ld/St instructions. 
rdar://problem/9269047


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129387 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 21:17:51 +00:00
Johnny Chen
f9ce2cba42 The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23} 
be specified as '1' (add = TRUE).

Also add a utility function for Thumb2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129377 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 18:48:00 +00:00
Johnny Chen
49fdfe3ce5 Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129365 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 17:09:04 +00:00
Cameron Zwarich
d0aacbcc2e Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARM 
stores of arguments in the same cache line. This fixes the second half of
<rdar://problem/8674845>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129345 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 02:24:17 +00:00
Johnny Chen
e77f72d7d2 A8.6.16 B 
Encoding T1 (tBcc)
if cond == '1110' then UNDEFINED;

rdar://problem/9268681


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129325 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 00:14:49 +00:00
Johnny Chen
de16508955 Thumb disassembler was erroneously rejecting "blx sp" instruction. 
rdar://problem/9267838


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129320 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 23:33:30 +00:00
Johnny Chen
35563fee7b Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled. 
rdar://problem/9266265


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129298 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 21:14:35 +00:00
Owen Anderson
78a546936d Fix another using-CPSR-twice bug in my ADCS/SBCS cleanups, and make proper use of the Commutable bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129294 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 20:12:19 +00:00
Johnny Chen
f18dfc3a31 Trivial comment fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129288 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 18:51:50 +00:00
Johnny Chen
e679d3331b Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as 
invalid instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129286 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 18:34:12 +00:00
Kevin Enderby
bd3327654b Adding support for printing operands symbolically to llvm's public 'C' 
disassembler API.  Hooked this up to the ARM target so such tools as Darwin's
otool(1) can now print things like branch targets for example this:
  blx _puts
instead of this:
  blx #-36
And even print the expression encoded in the Mach-O relocation entried for
things like this:
  movt r0, :upper16:((_foo-_bar)+1234)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129284 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 18:08:50 +00:00
Jay Foad
562b84b3ae Don't include Operator.h from InstrTypes.h. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129271 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-11 09:35:34 +00:00
Matt Beaumont-Gay
7c90e46622 Fix an apparent typo that made GCC complain 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129160 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 21:59:49 +00:00
Evan Cheng
4da0c7c0c9 Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is lowered into a call to the specified trap function at sdisel time. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129152 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 21:37:21 +00:00
Johnny Chen
ee10b13a44 Check opcoe (dmb, dsb) instead of bitfields matching. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129148 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 20:03:46 +00:00
Johnny Chen
c636074afc Hanlde the checking of bad regs for SMMLAR properly, instead of asserting. 
PR9650
rdar://problem/9257565


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129147 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 19:41:22 +00:00
Johnny Chen
40de2b3f15 Sanity check the option operand for DMB/DSB. 
PR9648
rdar://problem/9257634


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129146 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 19:18:07 +00:00
Jim Grosbach
5b03a3a59a Mark hasExtraDefRegAllocReq=1 on LDRD. 
The previous cleanup of LDRD got overzealous and removed it, causing post-RA
scheduling to get overzealous in breaking antidependencies and invalidate these instructions. Hilarity and invalid assembly ensued.

rdar://9244161


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129144 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 18:47:05 +00:00
Johnny Chen
97fdff1d3f Add sanity checking for bad register specifier(s) for the DPFrm instructions. 
Add more test cases to exercise the logical branches related to the above change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129117 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 00:29:09 +00:00
Evan Cheng
274d8d4eba Add option to emit @llvm.trap as a function call instead of a trap instruction. rdar://9249183. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129107 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 20:31:12 +00:00
Mon P Wang
e32cdef38e Fixed encoding for VEXTqf 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129101 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 19:56:12 +00:00
Johnny Chen
22dc4d9f59 Add sanity checking for invalid register encodings for signed/unsigned extend instructions. 
Add some test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129098 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 19:28:58 +00:00
Johnny Chen
8dbda0b51b Add sanity checking for invalid register encodings for saturating instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129096 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 19:02:08 +00:00